similar to: [LLVMdev] How to prevent generation of wide integers in LLVM IR?

On 01.07.2011 12:03, Eli Friedman wrote: > On Fri, Jul 1, 2011 at 12:53 AM, Корчагин Василий > <vasiliy.korchagin at gmail.com> wrote: >> Hello, LLVMdev. >> >> The problem is that C backend doesn't support integers wider than 64 >> bits, but I need to use it on programs with wide integers in LLVM IR. My >> question is how to deny LLVM to generate wide

On 1 July 2011 13:35, Vasiliy Korchagin <vasiliy.korchagin at gmail.com> wrote: > On 01.07.2011 12:03, Eli Friedman wrote: >> On Fri, Jul 1, 2011 at 12:53 AM, Корчагин Василий >> <vasiliy.korchagin at gmail.com>  wrote: >>> The problem is that C backend doesn't support integers wider than 64 >>> bits, but I need to use it on programs with wide

On Fri, Jul 1, 2011 at 12:53 AM, Корчагин Василий <vasiliy.korchagin at gmail.com> wrote: > Hello, LLVMdev. > > The problem is that C backend doesn't support integers wider than 64 > bits, but I need to use it on programs with wide integers in LLVM IR. My > question is how to deny LLVM to generate wide integer? Which part of > LLVM should I modify? scalarrepl is the

09.02.2011 18:57, Jason Kim пишет: > On Wed, Feb 9, 2011 at 5:02 AM, Vasiliy Korchagin > <vasiliy.korchagin at gmail.com> wrote: >> Hi, >> >> llvm emits code for "memcpy" on ARM as consecutive ldr/str commands, and > > Hmm, this happens elsewhere as well (x86?). Perhaps what we need is a > switch to disable memset/memcpy lowering? > Do you

-fno-builtin is the flag you want. deep On Wed, Feb 9, 2011 at 10:18 PM, Корчагин Василий <vasiliy.korchagin at gmail.com> wrote: > 09.02.2011 18:57, Jason Kim пишет: >> On Wed, Feb 9, 2011 at 5:02 AM, Vasiliy Korchagin >> <vasiliy.korchagin at gmail.com>  wrote: >>> Hi, >>> >>> llvm emits code for "memcpy" on ARM as consecutive

On Wed, Feb 9, 2011 at 5:02 AM, Vasiliy Korchagin <vasiliy.korchagin at gmail.com> wrote: > Hi, > > llvm emits code for "memcpy" on ARM as consecutive ldr/str commands, and Hmm, this happens elsewhere as well (x86?). Perhaps what we need is a switch to disable memset/memcpy lowering? > further combines them into ldm/stm with special pass after register >

07.02.2012 07:27, Eli Friedman пишет: > On Mon, Feb 6, 2012 at 6:51 PM, Xin Tong<xerox.time.tech at gmail.com> wrote: >> Is there any way to stop this ? >> >> /home/socrates/llvm/llvm-3.0.src/benchmarks/powerstone/crc/crc.c:67:1: >> error: 'main' must return 'int' >> void main() >> ^ >> 1 error generated. > You mean besides

Hi, llvm emits code for "memcpy" on ARM as consecutive ldr/str commands, and further combines them into ldm/stm with special pass after register allocation. But ldm/stm commands require registers to go in ascending order, what is often not so after regalloc, therefore some str/ldr commands. For example such code: struct Foo {int a, b, c, d; } void CopyStruct(struct Foo *a, struct

Is there any way to stop this ? /home/socrates/llvm/llvm-3.0.src/benchmarks/powerstone/crc/crc.c:67:1: error: 'main' must return 'int' void main() ^ 1 error generated. Thanks

On Mon, Feb 6, 2012 at 6:51 PM, Xin Tong <xerox.time.tech at gmail.com> wrote: > Is there any way to stop this ? > > /home/socrates/llvm/llvm-3.0.src/benchmarks/powerstone/crc/crc.c:67:1: > error: 'main' must return 'int' > void main() > ^ > 1 error generated. You mean besides fixing the source of your benchmark so it's valid C? Not at the moment...

It seems that one of the optimization passes (it seems to be SROA) sometimes transforms computations on vectors of ints to computations on wide integer types; for example, I'm seeing code like the following after optimizations(*): %0 = bitcast <16 x i8> %float2uint to i128 %1 = shl i128 %0, 8 %ins = or i128 %1, 255 %2 = bitcast i128 %ins to <16 x i8> The back end I'm

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi devs, I'd like to ask for some advise about optimization passes. Which pass might be responsible for this LLVM IR and why? %0 = load i288* bitcast ([9 x i32]* @array to i288*), align 16 %1 = lshr i288 %0, 224 array is just a global constant array of 9 integers and the code only accesses individual elements. The LLVM version is 3.1. Thanks,

The Scalar Replacement of Aggregates pass (-scalarrepl) generates these big integers. We recently added a constructor parameter to limit the size of the wide integer loads. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Mario Schwalbe Sent: Saturday, July 07, 2012 22:19 To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] Large

Hi Chris, Thanks for your reply. You said that scalarRepl gets shy about loads and stores of the entire aggregate. Then I use a test case: ; ModuleID = 'test1.ll' define i32 @fun(i32* nocapture %X, i32 %i) nounwind uwtable readonly { %stackArray = alloca <4 x i32> %XC = bitcast i32* %X to <4 x i32>* %arrayVal = load <4 x i32>* %XC store <4 x i32>

Hi all, I want to use scalarrepl pass to eliminate the allocation of mat_alloc which is of type [4 x <4 x float>] in the following program. $cat test.ll ; ModuleID = 'test.ll' define void @main(<4 x float>* %inArg, <4 x float>* %outArg, [4 x <4 x float>]* %constants) nounwind { entry: %inArg1 = load <4 x float>* %inArg %mat_alloc = alloca [4 x <4 x

Hi Fan, > You said that scalarRepl gets shy about loads and stores of the entire > aggregate. Then I use a test case: > > ; ModuleID = 'test1.ll' > define i32 @fun(i32* nocapture %X, i32 %i) nounwind uwtable readonly { > %stackArray = alloca <4 x i32> > %XC = bitcast i32* %X to <4 x i32>* > %arrayVal = load <4 x i32>* %XC > store

On Mar 10, 2012, at 9:34 AM, Fan Dawei wrote: > Hi all, > > I want to use scalarrepl pass to eliminate the allocation of mat_alloc which is of type [4 x <4 x float>] in the following program. > > $cat test.ll > > ; ModuleID = 'test.ll' > > define void @main(<4 x float>* %inArg, <4 x float>* %outArg, [4 x <4 x float>]* %constants)

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Hi all, I'm implementing a virtual processor which features dynamic register indexing, and I'm struggling to make LLVM 3.0 produce good code for it. The register set is implemented as an LLVM array so it can be dynamically indexed using GEP. However, most of the time the virtual processor's registers are just statically indexed, and so I expected/hoped the code would be as

Dear all, I am doing few experiments to do understand optimization phase interactions. Here is a brief description of my experiements. 1. I picked the list of machine independent optimizations acting on llvm IR (those that are enabled at O3). 2. for each optimzation in the optimization-list a) Compiled the program using 'clang -c O0 -flto program.c' b) opt