similar to: [LLVMdev] Instr Description Problem of MCore Backend

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

The parts of klibc specific to the alpha architecture. Signed-off-by: H. Peter Anvin <hpa at zytor.com> --- commit 5e5ce29210ac33a0b3704eb9ab5e5d5b55375575 tree 2ec24df596e13c21b68da4d905f546770d36fdad parent 8529b52550ba78984998d3a9cc9deb467217fa3e author H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun 2006 16:58:14 -0700 committer H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun

Hello! This is Kernel 2.4.6-ac1 with ext3-0.8.0 compiled with cvs-gcc version 3.1 20010616 on alpha ev4. I have prepared one ext3 filesystem to play with. When my rc-scripts call mount -a during boot I receive this: Jul 6 22:01:30 Marvin kernel: Bad unaligned kernel access at fffffc0000883f54: fffffc00063f2e6e 2a 2 and the mount of this filesystem fails. A subsequent manual second try to

Hi, I found that machine dead code elimination, does not respect the calling convention of alpha and eliminates r16, which was set correctly during code generation. I verified it with -print-after-all. Does anybody have a patch for this? On Wed, Jun 29, 2011 at 11:12 AM, Ankit Sethia <asethia at eecs.umich.edu>wrote: > Hi All, > > I am using llvm-2.9 to cross compile to alpha. I

Hi All, I am using llvm-2.9 to cross compile to alpha. I know that alpha is in experimental stage, but i can not get even the "Hello World" program to run on it. Here is what happens, the bitcode file for the hello world program is as follow: ; ModuleID = 'hello.bc' target datalayout =

Hi, Can people suggest how this is solved for other ISAs? This happens only for Alpha and not for x86-64. The register 16 does not have any uses within that function, but is used inside puts. So Machine DCE thinks it is dead code. On Wed, Jun 29, 2011 at 4:20 PM, Ankit Sethia <asethia at eecs.umich.edu>wrote: > Hi, > > I found that machine dead code elimination, does not respect

Hi LLVMers, I'm writing a LLVM backend for C*Core, an ISA derived from Motorola M*Core. I was wondering if someone wrote some IR level optimization passes for backend porting before ISel, such as an IR transformation from GEP to integer conversion/calculating instructions, and PHI combination. Here's the bubble sorting example. The IR codes below are changed by hand and I try to write

Hi All; I have a Dell M6400 with an NVIDIA Quadr FX 3700M card. Is there any way for me to setup 2 external monitors as opposed to one external monitor and the laptop screen? Thanks in advance

On Aug 28, 2007, at 6:15 PM, Scott Michel wrote: > On Aug 28, 2007, at 7:02 AM, Dan Gohman wrote: > >> On Mon, Aug 27, 2007 at 07:26:55PM -0700, Scott Michel wrote: >>> It looks like I need to be able to intercept GEP lowering (in >>> SelectionDAGLowering::visitGetElementPtr) and insert something else >>> other than the shifts and adds. The basic problem is

On Aug 28, 2007, at 7:02 AM, Dan Gohman wrote: > On Mon, Aug 27, 2007 at 07:26:55PM -0700, Scott Michel wrote: >> It looks like I need to be able to intercept GEP lowering (in >> SelectionDAGLowering::visitGetElementPtr) and insert something else >> other than the shifts and adds. The basic problem is that CellSPU >> loads and stores on 16-byte boundaries. Consequently,

Hi, I've been trying to get the python bridge (rpy2) to build for 64-bit R and python. The current stumbling block is that mingw can't use the python27.lib file that comes with CPython and so I need to generate libpython27.a. When I use dlltool from rtools to do that however, I end up with a 32-bit file: >"G:\Rtools\gcc-4.6.3\i686-w64-mingw32\bin\dlltool" -e libpython27.a

[A repost under a new topic since the other seems to have been lost in the noise] I am basically down to one unresolved compilier diagnostic. The HP/COMPAQ/DEC C compiler is concerned about this line in TOKEN.C 4 22136 temp_byte = (char) n >> 8; ........................................1 %CC-I-RIGHTSHIFTOVR, (1) In this statement, the right shift count

The G.729.1 "wideband" codec is starting to show a slight bit of traction. There is a possibility that Asterisk could support G.729.1 - would you use it or buy it if it was available? More importantly, does any equipment with which your systems currently exchange traffic support G.729.1? Currently, the number of devices supporting G.729.1 seems to be fairly limited and it

I am applying classification methods to a dataset with 2 classes; where y=0 - non survival and y=1 - survival. When using ldq, qda, glm, gam ,etc. y=0 is assigned as class 1 and y=1 is assigned as class 0. How can I always assign y=0 as class 0 and y=1 as class 1? Thank you for your time, Heather Thiessen -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.- r-help

On Mon, 28 Jun 2004, Surupa Biswas wrote: > I am at the University of Maryland, College Park, working with Prof. > Rajeev Barua. Someone just told me that LLVM includes a C++ to C > source-to-source compiler. I was hoping you could tell me something about > that - I am trying to run some C++ benchmarks on the Motorola Mcore > simulator and my compiler only has a C front-end. Yup,

We're running samba 2.0.7 on an alphalinux machine (kernel 2.2.16, this is redhat-alpha 6.0, if that's important) and nmbd is crashing with an internal error. See the logs below (log.nmb at the bottom). I'd do some checking around on the samba mailing list archives, but they've been down for some time now. nmbd generates this message on startup. When I ran it from the shell

The VMI ROM detection and code patching mechanism is illustrated in setup.c. There ROM is a binary block published by the hypervisor, and and there are certainly implications of this. ROMs certainly have a history of being proprietary, very differently licensed pieces of software, and mostly under non-free licenses. Before jumping to the conclusion that this is a bad thing, let us consider more

The VMI ROM detection and code patching mechanism is illustrated in setup.c. There ROM is a binary block published by the hypervisor, and and there are certainly implications of this. ROMs certainly have a history of being proprietary, very differently licensed pieces of software, and mostly under non-free licenses. Before jumping to the conclusion that this is a bad thing, let us consider more

On Mon, Aug 27, 2007 at 07:26:55PM -0700, Scott Michel wrote: > It looks like I need to be able to intercept GEP lowering (in > SelectionDAGLowering::visitGetElementPtr) and insert something else > other than the shifts and adds. The basic problem is that CellSPU > loads and stores on 16-byte boundaries. Consequently, the SPU backend > has to do the load or store differently

Andrea_DiBiagio at sn.scee.net wrote: > So.. > I have investigated more on how a new function attribute to disable > optimization on a per-function basis could be implemented. > At the current state, with the lack of specific support from the pass > managers I found two big problems when trying to implement a prototype > implementation of the new attribute. > > Here are the