similar to: [LLVMdev] Fwd: instruction description

On Tue, May 24, 2011 at 8:35 AM, roy rosen <roy.1rosen at gmail.com> wrote: > 2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > >> > >> Hi, > >> > >> I was wondering if LLVM supports predicates and conditional execution. > >>

2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: >> >> Hi, >> >> I was wondering if LLVM supports predicates and conditional execution. >> Something like we have in IA64. >> There is a register class of predicates and then every instruction may >> be

I think we can mark this bug closed and check in the patch. Anyone have any concerns/questions before I do? Roy -------- Original Message -------- Subject: [ wxruby-Bugs-6144 ] error: cast from ?void*? to ?int? loses precision Date: Sun, 15 Oct 2006 08:37:31 -0400 (EDT) From: <noreply at rubyforge.org> To: noreply at rubyforge.org Bugs item #6144, was opened at 2006-10-15 00:04

On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > Hi, > > I was wondering if LLVM supports predicates and conditional execution. > Something like we have in IA64. > There is a register class of predicates and then every instruction may > be predicated by a register from this class. > For example: > > cmp_less p, x, y // p is a predicate

If liveness analysis indicates it's good, this should improve the chances of being able to emit the short MAD form. Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp

From: Joerg Roedel <jroedel at suse.de> Factor out the code used to decode an instruction with the correct address and operand sizes to a helper function. No functional changes. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/asm/insn-eval.h | 2 ++ arch/x86/kernel/umip.c | 23 +--------------- arch/x86/lib/insn-eval.c | 45

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add instruction Is there support in LLVM to something

Thanks David, It is working. Holtman's also gave me a solution but, I wanted to have a color pallet for description of colors, that was not in his solution. However I need one small modification. If I want to plot only lower diagonal elements of 'dat' then how should I proceed? What I want is, to visualize only lower diagonal elements and having the color pallet on them only. Also

Forwarded from the SWIG mailing list, so we have a copy in our archives. Kevin -------- Original Message -------- Subject: Re: [Swig] Re: Object return problem Date: Sun, 09 Oct 2005 18:31:40 -0400 From: Kevin Smith <wxruby@qualitycode.com> To: Charlie Savage <cfis@interserv.com> CC: Swig@cs.uchicago.edu References: <4347277E.1030700@mindspring.com>

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

From: Joerg Roedel <jroedel at suse.de> When a #VC exception is triggered by user-space the instruction decoder needs to read the instruction bytes from user addresses. Enhance vc_decode_insn() to safely fetch kernel and user instructions. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/kernel/sev-es.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22

Hi.? There appears to be a bug in R function manova.? My friend and I both ran it the same way as shown below (his run) with the shown data set. His results are shown below. we both got the same results.? I was running with R 2.3.1. I'm not sure what version he used. Thanks very much, David Booth Kent State University -----Original Message----- From: dvdbooth at cs.com To: kberk at

On Sun, 1 Oct 2006, Roman Levenstein wrote: > I'm trying to implement a new backend for an embedded CISC processor. > Therefore I thought that it makes sense to take X86 target as a basis, > to save some time. Ok. Note that the X86 backend is one of the most complex though, because it supports several subtargets and ABIs, which makes it more complex than some other targets. >

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Pretty sure there's nothing wrong with it, but it looks odd in the code. src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++ src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++-- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-)

Crossbow team, The following is of interest to the Crossbow project. Since a large chunk of these changes also exist in the Crossbow gate, the delivery of this wad will result in fewer lines of changes for Crossbow''s delivery. If someone on Crossbow could participate in this review, that would be a bonus (Eric Cheng made original changes in the Crossbow gate at some point last year).

On 08/26/2010 13:17, Dale Johannesen wrote: >>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, >>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >> >> Odd. I thought TCReturn was being lowered. At any rate can you file >> a bug with the .ll file that causes this? > > It should be getting

The only multiplication instruction on my target CPU is multiply-and-accumulate. The result goes into a special register that can destructively read at the end of a sequence of multiply-adds. The following sequence is required to so a simple multiply: acc r0 # clear accumulator, discarding its value (r0 reads as 0, and sinks writes) mac rSRC1, rSRC2 # multiply sources, store

(Mostly for Roy): I saw this on the SWIG list, and wonder if it might be related to the problems we have been seeing where multi-arg typemaps end up invoking the wrong wrapper methods. (Not the newly-discovered directorout stuff). Perhaps if we switched to "compactdefaultargs" things would start to work more sanely. Looking at this section of the SWIG docs, it looks like it should

On Apr 16, 2009, at 2:19 PM, Greg McGary wrote: > The only multiplication instruction on my target CPU is > multiply-and-accumulate. The result goes into a special register that > can destructively read at the end of a sequence of multiply-adds. The > following sequence is required to so a simple multiply: > > acc r0 # clear accumulator, discarding its value (r0 reads as

Take a look at this message thread. I think it would be interesting/nice if our constants and enums also returned a nice name when inspected. Thoughts? Roy -------- Original Message -------- Subject: Re: [Swig-user] wrapping enums for python Date: Wed, 13 Sep 2006 17:14:50 +0200 From: Nitro <nitro@dr-code.org> To: K M <intra611@gmail.com>, swig-user@lists.sourceforge.net