similar to: [LLVMdev] [MIPS] some type errors in the commentary of *.td file.

On May 7, 2011, at 2:47 AM, Liu wrote: > On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote: >> >> On May 5, 2011, at 11:26 PM, Liu wrote: >> >>> some some type errors in the commentary of *.td file. >>> such as: >>> lib/Target/Mips/MipsInstrFormats.td >>> MipsRegisterInfo.td - Mips Register defs

On Sat, May 7, 2011 at 12:33 PM, Eric Christopher <echristo at apple.com> wrote: > > On May 5, 2011, at 11:26 PM, Liu wrote: > >>  some some type errors in the commentary of *.td file. >> such as: >> lib/Target/Mips/MipsInstrFormats.td >> MipsRegisterInfo.td - Mips Register defs >> it should be >> MipsInstrFormats.td - Mips Instruction Formats

On May 5, 2011, at 11:26 PM, Liu wrote: > some some type errors in the commentary of *.td file. > such as: > lib/Target/Mips/MipsInstrFormats.td > MipsRegisterInfo.td - Mips Register defs > it should be > MipsInstrFormats.td - Mips Instruction Formats > > lib/Target/Mips/MipsInstrInfo.td > MipsInstrInfo.td - Mips Register defs > it should be > MipsInstrInfo.td -

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? For the Mips platform we create the following .inc files through tblgen. tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)

Hi Jack, On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create

On 04/01/2013 12:31 PM, Chandler Carruth wrote: > On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com > <mailto:nrotem at apple.com>> wrote: > > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if > the attributes changed). Do you have another solution in mind ?

At least or Mips, this line seems extraneous. I removed it and and all consequential uses of that (400 changes to MipsRegisterInfo.td) and make check for mips still works. Am running our full test sequence now. This Mips part of this was copied from the Sparc port. Similar problems in other ports. Seems this has just been copied many times to new ports. On 03/21/2012 02:58 PM, reed kotler

On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for

Hi, I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that

I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken. -Jim On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > Hi, > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, > > > > On Thu, Oct 6, 2011 at

Hello Anton. Thanks for the comment. > Precisely this is the situation! There're two consecutive branches (br1cond >> and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond >> (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by >> br2uncond->eraseFromParent(). This results in br1cond loosing it's >>

I don't think I ever said that the MIPS target is broken. I am simply trying to branch out one additional llc target for SimpleScalar PISA architecture. On Fri, Oct 7, 2011 at 2:41 PM, Jim Grosbach <grosbach at apple.com> wrote: > I reiterate. You should fix the simulator. It is broken. The compiler is > not. Fix what's broken. > > -Jim > > On Oct 7, 2011, at 1:11

What is the purpose of tablegen created files for fast-isel? If I make the following change to Makefile in lib/Target/Mips BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ +

The field Num seems to have no meaning. It is not recognized by the backend tools. It does not hurt anything but should not be there. // We have banks of 32 registers each. class MipsReg<string n> : Register<n> { field bits<5> Num; let Namespace = "Mips"; } class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {

>> br2uncond->eraseFromParent(). This results in br1cond loosing it's >> label/offset. How could I resolve this? > Your code is broken. AnalyzeBranch should not modify anything. > > I was taking a clue from Mips/MipsInstrInfo.cpp: AnalyzeBranch :( > Could you please suggest appropriate alternative place for such a > modification? Ah sorry, my memory served me

YOu have to look for which DAG fragments are not being matched. Then you can create patterns for those using alternate sequences. When you disablea given instruction, don't just disable it, but also look at what pattern it was matching. Then create a patten for that using remaining instructions or in some cases you might have to call a library function, as in the case of floating

Hello David, Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR instruction of "set" in "LLVM Language Reference Manual". Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is

Sorry, I meant to say, I added code to prevent llc from running machine verifier after delay slots are filled. MipsInstrInfo::AnalyzeBranch generates incorrect results after delay slots are filled. Also, it seems that code in MachineVerifier.cpp wasn't written with architectures that have delay slots in mind. On Wed, Apr 25, 2012 at 11:59 AM, Akira Hatanaka <ahatanak at gmail.com>

I'm trying to build a standalone assembler for Mips using AsmParser. Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. I am getting an assertion for what I believe are multiple register definitions with the same name. llvm-tblgen:

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or