similar to: [LLVMdev] mblaze backend: unreachable executed

Hello, Am 15.03.2011 um 19:27 schrieb Josef Spjut: > Does anyone know what common causes of "UNREACHABLE executed!" > messages are and what this message in particular means? The full > error message is the following: > > UNREACHABLE executed! > 0 llc 0x0000000100936ae2 PrintStackTrace(void*) + 34 > 1 llc 0x0000000100937603

> what does "refuses to compile" mean? I.e. what error do you get? > Specifically I get this message when compiling with the default -mattr: Call result #2 has unhandled type i32 UNREACHABLE executed at CallingConvLower.cpp:162! 0 llc 0x0000000100a1e115 PrintStackTrace(void*) + 38 1 llc 0x0000000100a1e6d0 SignalHandler(int) + 254 2

Hi Josef, > Okay, I've done a lot more testing and I now have a .bc file that compiles for x86, sparc, mips but refuses to compile for the mblaze and powerPC backends because of the calling convention. Is there anyone that would know how to fix the microblaze calling convention or point me in the right direction on how to fix it? what does "refuses to compile" mean? I.e. what

> > what does "refuses to compile" mean? I.e. what error do you get? > Specifically I get this message when compiling with the default -mattr: Call result #2 has unhandled type i32 UNREACHABLE executed at CallingConvLower.cpp:162! 0 llc 0x0000000100a1e115 PrintStackTrace(void*) + 38 1 llc 0x0000000100a1e6d0 SignalHandler(int) + 254 2

hi all I have a question about implementing a new instruction which does this function f(x) = x + ceilf (x) .x is a single float i have already added the instruction in my backend in the .td file def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; it makes

Hi, > def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), > "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 > (ceilf FGR32:$fs))))] >; > > it makes and install correctly but when i ll try to write code to use this > instruction there is no luck. More details (including the .ll source and *how* exactly things are

>I'm also a little worried that your pattern has fadd, but your C >source has a subtraction. :S i wrote it wrong the true implementation is def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fsub (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; I use some C,C++ code to test my backend. i use clang

On May 22, 2012, at 8:05 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. > In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. > For example ceil.w.s

I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. For example ceil.w.s means both source and destination are F32 registers while ceil.l.d means both source and destination are F64

On Tue, Sep 25, 2018 at 7:37 PM Sanjay Patel <spatel at rotateright.com> wrote: > > > On Tue, Sep 25, 2018 at 2:28 PM Cameron McInally <cameron.mcinally at nyu.edu> > wrote: > >> On Tue, Sep 25, 2018 at 1:39 PM Sanjay Patel <spatel at rotateright.com> >> wrote: >> >>> I have 1 concern about adding an explicit fneg op to IR: >>>

Do we really want to have fneg be the only instruction with guaranteed no side effects? That just sounds like a gotcha waiting to happen. Or it could result in horrible code depending on the architecture. I’m still leaning towards having both an intrinsic and an instruction, and if they happen to have the same behavior then that’s fine. If fneg is to be a special instruction with extra promises

+1 for an explicit FNEG instruction, since as previously discussed, it has stricter requirements for what value may be returned by the operation. And strengthening the requirement on FSUB is not feasible when the values are variables rather than literals. That is: FSUB(-0.0, NaN) = either NaN *or* -NaN FSUB(-0.0, -NaN) = either NaN *or* -NaN FNEG(NaN) = -NaN FNEG(-NaN) = NaN On Tue, Sep 11,

On Tue, Sep 25, 2018 at 1:39 PM Sanjay Patel <spatel at rotateright.com> wrote: > I have 1 concern about adding an explicit fneg op to IR: > > Currently, fneg qualifies as a binop in IR (since there's no other way to > represent it), and we have IR transforms that are based on matching that > pattern (m_BinOp). With a proper unary fneg instruction, those transforms >

Regarding non-IEEE targets: yes, we definitely support those, so we do have to be careful about not breaking them. I know because I have broken them. :) See the discussion and related links here: https://reviews.llvm.org/D19391 But having an exactly specified fneg op makes that easier, not harder, as I see it. Unfortunately, if a target doesn't support this op (always toggle the sign bit and

On Tue, Feb 5, 2013 at 12:52 PM, Chandler Carruth <chandlerc at gmail.com>wrote: > The MBlaze backend seems to be essentially unmaintained since 2011. The > maintainer (Wesley Peck who is BCC'ed) seems to have vanished, and in fact > all emails to him are bouncing. > > I propose to remove the MBlaze backend on Friday if none step forward as a > maintainer. Currently,

On Feb 6, 2013 4:52 AM, "Chandler Carruth" <chandlerc at gmail.com> wrote: > > The MBlaze backend seems to be essentially unmaintained since 2011. The maintainer (Wesley Peck who is BCC'ed) seems to have vanished, and in fact all emails to him are bouncing. > > I propose to remove the MBlaze backend on Friday if none step forward as a maintainer. Currently, folks

> > The MBlaze backend seems to be essentially unmaintained since 2011. The > maintainer (Wesley Peck who is BCC'ed) seems to have vanished, and in fact > all emails to him are bouncing. > I propose to remove the MBlaze backend on Friday if none step forward as a > maintainer. Currently, folks are having to keep it up to date when changing > shared parts of the backend

Eli, I've been working on this for a few days and still haven't gotten this towork. I've attached my dags that you asked for, and even there it is turning the floating point instruction into an integer return value. IR code just for reference: -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Villmow, Micah Sent:

On Tue, Feb 5, 2013 at 3:50 PM, Preston Briggs <preston.briggs at gmail.com>wrote: > The MBlaze backend seems to be essentially unmaintained since 2011. The >> maintainer (Wesley Peck who is BCC'ed) seems to have vanished, and in fact >> all emails to him are bouncing. > > >> I propose to remove the MBlaze backend on Friday if none step forward as >> a

On Mar 15, 2011, at 1:50 PM, Andreas Färber wrote: > Hello, > > Running the Debug+Asserts version instead of the Release should give you the file and line of the "unreachable" code. > > Andreas Thanks for the suggestion. I recompiled with Debug+Asserts and it shows that the unreachable is in CallingConvLower.cpp:162. Here is the error message: Call result #2 has