similar to: [LLVMdev] Question about TableGen when adding LLVM Backend.

On Mar 9, 2011, at 2:13 PM, Lu Mitnick wrote: > Hello all, > > I have some question about usage of TableGen when adding a new LLVM Backend. There are three place to use TableGen in basic steps of document "Writing an LLVM Compiler > Backend": > > 2. Describe the register set of the target. Use "TableGen" to generate code for register definition, register

Hello Jakob, Is this means that TableGen execution is handled in Makefile. Porting programmer doesn't need to execute TableGen by hand? thanks 2011/3/10 Jakob Stoklund Olesen <stoklund at 2pi.dk> > > On Mar 9, 2011, at 2:13 PM, Lu Mitnick wrote: > > > Hello all, > > > > I have some question about usage of TableGen when adding a new LLVM > Backend. There

Dear all. I have a problem with the following situation: I want to handle an intrinsic function in a specific way. The prototype of my function is: "/int my_intrinsic_name()/" So I want to generate a move instruction which should use two register type operands: "/mov R1, R2/" For this purpose I assume that the instruction definition in the TargetInstrInfo.td file

Hello all, I am adding a new target into LLVM. However there is a assembler for that target and I just want LLVM to generate assembly. I read the document "Writing an LLVM Backend". I am wondering to know whether I can ignore the Inst field in the following example: class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32>

i have loop index I. I want to increment it by 1. How to do this in registerinfo.td. I m trying following but getting error. let SubRegIndices = [sub_32bit, sub_32bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-255 in { m=add(I,1); def R_#J#_REG64b_#I : R_P<"R_"#J#"_R64b_"#I, !shl(I,2), [!cast<R_P>("R_"#J#"_REG32b_"#I),

On Mar 9, 2011, at 8:15 PM, Lu Mitnick wrote: > Hello Jakob, > > Is this means that TableGen execution is handled in Makefile. Porting programmer doesn't need to execute TableGen by hand? That's right. You are going to be editing your .td files a lot, so you want that integrated in the build system.

Am 10.03.2011 um 05:35 schrieb Jakob Stoklund Olesen: > On Mar 9, 2011, at 8:15 PM, Lu Mitnick wrote: > >> Hello Jakob, >> >> Is this means that TableGen execution is handled in Makefile. >> Porting programmer doesn't need to execute TableGen by hand? > > That's right. > > You are going to be editing your .td files a lot, so you want that >

Lu Mitnick <king19880326 at gmail.com> writes: > Hello all, > > I am adding a new target into LLVM. However there is a assembler for > that target and I just want LLVM to generate assembly. I read the > document "Writing an LLVM Backend". I am wondering to know whether I > can ignore the Inst field in the following example: I'm not an expert here so I'll

Hello all, I am willing to do "eliminating the void type" project. Is there anyone working on it? === Overview === The general concept is to replaced void with {}. And 'ret void' is a synonym of 'ret {} {}.' === Further Implementation Details === 1. Deleting VoidTyID 2. Deleting LLVMVoidTypeKind (one-to-one relation between VoidTyID and LLVMVoidTypeKind) 3. Use

On Mon, Sep 15, 2008 at 4:51 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > With my backend code gen I want to assign calling parameters to a list of > registers, but since I'm targeting a virtual instruction set. I don't want > to be limited by the number of registers. Is there a way using TableGen to > specify just a starting register to assign to for the

Hello all, I have read the chapter "Writing an LLVM Pass" and noticed that there is a topic "Multithreaded LLVM". However I have no idea about this. I am wondering to know whether the goal of this extension is: 1. Multiple threads handle different modules (Thread : Module = 1 : 1) or 2. Multiple threads handle one module (Thread : Module = N : 1) Thanks a lot --------------

Hello Everyone, I am trying to make a new LLVM backend target for Intel GPU. I would start from targeting OpenCL language first. But I am not quite familiar with LLVM backend infrastructure. I have some problem on describing the RegisterInfo. Intel GPU launches lots of hardware threads to do GPGPU workload. Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte. Each

Hi, Regarding the mischeduler, I wonder // For loops that are acyclic path limited, aggressively schedule for // latency. This can result in very long dependence chains scheduled in // sequence, so once every cycle (when CurrMOps == 0), switch to normal // heuristics. if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() && tryLatency(TryCand, Cand, *Zone))

With my backend code gen I want to assign calling parameters to a list of registers, but since I'm targeting a virtual instruction set. I don't want to be limited by the number of registers. Is there a way using TableGen to specify just a starting register to assign to for the CallingConv class and then have it just use sequential registers? Micah Villmow Systems Engineer Advanced

I have made changes in 3 files: LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached here. Now i am getting following errors. which means registerinfo.inc file is not generated successfully. /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: no member named 'XMM8' in namespace 'llvm::X86' if ((RegNo >= X86::XMM8 && RegNo <=

Hello Krzysztof, The R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > I tried reproducing the problem, but the file

This proposal adds support for path profiling [Ball96] to LLVM. Path profiling compactly represents acyclic paths in a directed acyclic graph representation of the control flow graph of a routine. Instrumentation can be added to uniquely identify paths executed at runtime. Path profiles enable precise enumeration of the sequence of basic blocks executed in order for a particular path. Using path

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&

Hi Mitnick, > === Overview === > > The general concept is to replaced void with {}. And 'ret void' is a synonym of > 'ret {} {}.' in a sense the concept is just to delete void and not to replace it with anything in particular. Of course front-ends (clang, dragonegg) need to produce something instead of void, and {} is an example of what they might produce, but they

Hello all, I noticed Eliminating the 'void' type<http://nondot.org/sabre/LLVMNotes/EliminatingVoid.txt>in Random LLVM notes. I am wondering to know what's the meaning of "eliminating" the void type. Is it means the goal is deleting VoidTyID from TypeID enumeration in Type.h? And what Type::getVoidTy() returned is a pointer to a {}? Thanks Mitnick -------------- next