Displaying 20 results from an estimated 20000 matches similar to: "[LLVMdev] readonly registers"
2011 Feb 22
1
[LLVMdev] virtual register does not exist
Hi
is there a way to know later that an earlier pass inside the codegen
might have eliminated a virtual register.
I carry information abt virtual registers which i would like to update
if any virtual register does not exist since.
thanks
dz
2011 Jan 09
2
[LLVMdev] Increasing TargetRegisterInfo::FirstVirtualRegister?
On Jan 7, 2011, at 11:25 AM, Dale Johannesen wrote:
> We might want to make physical registers negative and virtuals positive, or vice versa. Then FirstVirtualRegister is 0 or 1, and we could get rid of those annoying subtractions of FirstVirtualRegister all over the virtual-register-handling passes. Since 0 is used all over the place as "invalid register" it is probably best to
2011 Jan 06
1
[LLVMdev] Pass to compute livein info
Hi all,
Is there a pass that computes livein information for each
MachineBasicBlock? I tried to find such a pass but could not find any. I
am trying to use the livein information to get dead registers to insert
some instructions right before code emission but the livein information
seems to be invalidated by some pass. I might need to recompute the
livein information before my pass. Thanks a
2010 Dec 29
1
[LLVMdev] stack alignment restriction
Thanks for the answer..
A followup question - Is this already taken into consideration when
generating address calculation offset etc or would this need to be
specially taken care?
I am assuming all load/stores also would need to be custom lowered.
thanks
dz
On Wed, Dec 29, 2010 at 5:45 AM, Bill Wendling <wendling at apple.com> wrote:
> On Dec 28, 2010, at 4:02 PM, drizzle drizzle
2010 Dec 29
2
[LLVMdev] stack alignment restriction
Hi
Is there a way to enforce a different alignment on vales on stack
as compared to other basic types. Particularly, i would like
characters to be stored at 2 byte boundary.
thanks
dz
2011 Mar 02
3
[LLVMdev] live variable analysis
Hi
As I understand live variable analysis will set the def/kill
properties of operands. In that case, is it still needed to set the
kill flags when possible during lowering?
thanks
dz
2011 Jan 07
0
[LLVMdev] Increasing TargetRegisterInfo::FirstVirtualRegister?
We might want to make physical registers negative and virtuals positive, or vice versa. Then FirstVirtualRegister is 0 or 1, and we could get rid of those annoying subtractions of FirstVirtualRegister all over the virtual-register-handling passes. Since 0 is used all over the place as "invalid register" it is probably best to leave this alone, let FirstVirtualRegister be 1, and simply
2011 Jan 29
1
[LLVMdev] The type or size of virtual registers in machineinstr
Hi,
I want to know what is the type or size of a virtual register in a
Machineinstr::MachineOperand (If this MachineOperand is a register). For
example, what is the size of reg16385 in the following MachineInstr. I know
now in the llvm bitcode, the type of a Instruction could be obtained from
the Value::GetType(), but what is the counterpart in MachineInstr (not
derived from class Value)?
2011 Jan 07
3
[LLVMdev] Increasing TargetRegisterInfo::FirstVirtualRegister?
On 01/07/2011 02:07 AM, Chris Lattner wrote:
>
> Unless your goal is to merge this work onto LLVM mainline, the best thing to do is a local hack in your tree.
>
> -Chris
Yes, I will create a patch for my tree to increase
FirstVirtualRegister. Would this be a good change to include in 2.9?
2010 Jul 21
2
[LLVMdev] Spilling multi-word virtual registers
On Tuesday, July 20, 2010 4:04 PM, Jakob Stoklund Olesen
>
> On Jul 20, 2010, at 10:57 AM, Ken Dyck wrote:
>
> > Does anybody have any tips for generating spills/reloads for large
> > non-vector registers?
> > [snip]
>
>
> This is quite simple to handle. A register
> MachineOperand has a subreg field for this
> purpose. It is used to pick out subregisters
2011 Jan 08
1
[LLVMdev] i64 type in optimizer
Hi
Is there way to prevent i64 values being generated by the optimizer ?
thanks
dz
2010 Jun 08
0
[LLVMdev] Heads up: Local register allocator going away
On Fri, 2010-06-04 at 20:05 +0200, Jakob Stoklund Olesen wrote:
> You should fix SPUTargetLowering::LowerCall to make sure there is an unbroken chain of flag ties between CopyFromReg and BRASL. At least ARM, MBlaze, and Blackfin are doing this, if you need example code.
>
Thanks for the tip. This got fixed in 105601.
And with that, half of the problematic tests appearing with
2010 Sep 25
2
[LLVMdev] What's up with the buildbots?
It looks like they are not starting new builds automatically any more.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/pkcs7-signature
Size: 1929 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100924/65f313de/attachment.bin>
2010 Oct 20
3
[LLVMdev] llvm register reload/spilling around calls
Thanks for giving it a look!
On 19.10.2010 23:21, Jakob Stoklund Olesen wrote:
> On Oct 19, 2010, at 11:40 AM, Roland Scheidegger wrote:
>
>> So I saw that the code is doing lots of register
>> spilling/reloading. Now I understand that due to calling
>> conventions, there's not really a way to avoid this - I tried using
>> coldcc but apparently the backend
2010 Jun 04
2
[LLVMdev] Heads up: Local register allocator going away
On Jun 4, 2010, at 1:57 AM, <Kalle.Raiskila at nokia.com> <Kalle.Raiskila at nokia.com> wrote:
> On Thu, 2010-06-03 at 02:53 +0200, Jakob Stoklund Olesen wrote:
>> If you are using the local register allocator, please try switching to the fast allocator and report any bugs you find.
>>
> Tried it, and it seems to break quite a big chunk of our tests on SPU :)
2012 Apr 18
0
[LLVMdev] Conceptual difference between "Unallocatable" and "Reserved" registers.
On Apr 17, 2012, at 9:09 PM, Lei Mou wrote:
> I'm writing to ask the differences between a "reserved" register and an "unallocable" register. In X86 backend, for example, the stack pointer register and instruction pointer are reserved but allocatable. In the Doxygen document of function llvm::TargetRegisterInfo::getReservedRegs, it says that a reserved register is one
2011 Jan 16
1
[LLVMdev] About register allocation
I have tested the register allocation in llvm, using: $llc -debug test.bc
where, test.c is like:
int a, b, c, d, x;
a = 3;
b = 5;
d = 4;
x = 100;
if ( a > b )
......
And I got the machine code before register allocation:
MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a]
MOV32mi <fi#3>, 1, %reg0, 0, %reg0,
2010 Sep 08
0
[LLVMdev] Possible missed optimization?
Great analysis Jakob, should this be reported as a missed optimization or
are you going to handle this as you're the register allocator expert here?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100908/7fb8471e/attachment.html>
2010 Dec 06
3
[LLVMdev] using bugpoint
I would like to use bugpoint to debug some of my passes. I have read the
documentation, but I don't completely understand it.
I have a bitcode file X.bc that I transform using the following commands:
opt -mypass1 -f -o X.1.bc X.bc // transform with mypass1
llvm-link -f -o X.2.bc X.1.bc support.bc // link with support.bc
opt -mypass2 -f -o X.3.bc X.2.bc // transform with mypass2
After
2010 Dec 19
2
[LLVMdev] About the information about live variable analysis
Hi,
I worked in llvm to get some information from live variable analysis.
If the live range of one variable interferes with another, we could record
the related two variables into a pair. For example, with a function with
local variables 'a', 'b', 'c', 'x' and 'y', the pair set { (a, b), (b,c),
(x,y)} indicates that 'a' interferes with 'b',