similar to: [LLVMdev] About the information about live variable analysis

On Dec 18, 2010, at 5:53 PM, Qingan Li wrote: > Hi, > > I worked in llvm to get some information from live variable analysis. > If the live range of one variable interferes with another, we could record the related two variables into a pair. For example, with a function with local variables 'a', 'b', 'c', 'x' and 'y', the pair set { (a, b),

Hal's advice helps me a lot to understand the implementation much better. Thanks so much! So, now I am able to state my problem more clearly: 1) There are two kinds of locals, i.e., the local variables originated from the source code (like C/C++), and the compilation generated temporaries. After instruction selection phase, the former is seen as frame indexes, while the latter is seen as

Hi, Can anyone help me with the stack slot coloring optimization? This corresponding file is /lib/codegen/stackslotcoloring.cpp. It is said this optimization was for stack slot overlay for frame size reduction, after register allocation phase. And this transformation pass relies on the LiveStack analysis pass. How, when checking the source code, it seems the LiveStack analysis has not been

Hello to all. I'm trying to implement a simple register allocator using graph colouring (I know, everyone has already done that :-)) and I'm also using LLVM 3.4 from master branch. The algorithm I'm using is based on the one described on the "Modern Compiler Implementation in C". My implementation is totally experimental and doesn't aim to be fast, eficient or even

---------- Forwarded message ---------- From: Qingan Li <ww345ww at gmail.com> Date: 2011/5/30 Subject: To: llvmdev at cs.uiuc.edu Hi, I wrote an analysis pass, myPass, inherited from both ModulePass and ProfileInfo, and this pass requires the CallGraph, i.e., * class myPass : public ModulePass, public ProfileInfo { ...};* * void myPass::getAnalysisUsage(AnalysisUsage &AU) const

On Sep 17, 2013, at 5:15 AM, Leandro Santiago <leandrosansilva at gmail.com> wrote: > Hello to all. I'm trying to implement a simple register allocator using graph colouring (I know, everyone has already done that :-)) and I'm also using LLVM 3.4 from master branch. > > The algorithm I'm using is based on the one described on the "Modern Compiler Implementation in

When I searched for branch frequency profiling on the internet, I got this link by a casual chance: http://homepages.dcc.ufmg.br/~rimsa/tools/stprof-llvm.patch. It seems it was written by Andrei Rimsa. So I downloaded and integrate these files into the llvm-2.8 building. After the building, I tried "opt -static-profile bitcnt_1.bc", and an segment fault error occured. I debugged it

*1. I have searched the access/setting of LLVMCC_EMITIR_FLAG in the build directory, recursively, and all the output is what I pasted in last email (just the same to the that in source directory). Maybe the configure failed to do it. My command list for building the test suit is as followings:* *(1) cd ~/SRC_DIR/llvm/projects* *(2) svn co http://llvm.org/svn/llvm-project/test-suite/trunk

---------- Forwarded message ---------- From: Qingan Li <ww345ww at gmail.com> Date: 2011/1/19 Subject: Re: [LLVMdev] About test suits Cont1 To: Eric Christopher <echristo at apple.com> *I am sorry for making you confused when I presented my problem.* *1. My steps for the test suit building:* (1) cd /home/qali/Src; * // This is my source directory for all application

Thanks for your help with me about the way to access type and size of Value. But, I want also know the interface for me to access the type or size of virtual registers in the SSA form. 1. I find no way to associate the virtual registers with the Value class. 2. I also tried to get the size of register nReg by: TargetRegisterClass::getSize(), where the TargetRegisterClass object is obtained by

On 1/28/11 8:14 AM, Qingan Li wrote: > Thanks for your help with me about the way to access type and size of > Value. > But, I want also know the interface for me to access the type or size > of virtual registers in the SSA form. > 1. I find no way to associate the virtual registers with the Value class. In the in-memory LLVM IR, all of the SSA values are C++ objects derived

Hi Li Qingan, > Thanks for your last reply. > I have made a critical mistake when I stated my question in last email. > I built llvm in debug mode, but the NDEBUG seemed to be still defined, such that > the -debug option is not enabled. > I have restated my configuration below. you need to configure with --enable-assertions In spite of the name, NDEBUG is not related to

Thanks for your last reply. Could I understand the way to adding a pass (built into the llvm rather than dynamic loadable) includes: 1. Declaring a creator function for this pass 2. Implementing the creator function for this pass 3. Instantiating this pass and get a object of it 3. Register this pass into the PassRegistry Then, for a built-into bytecode pass, task 1(declaration of the

Toward a better register allocator, I'm attempting to understand the dataflow information available to the allocator. What's the difference between LiveInterval information and LiveVariable information? If a LiveInterval is based on a linear ordering of the machine instructions, isn't it rather conservative in nature? Let's say I have a typical diamond CFG: A

llvm::TargetRegisterClass::getSize() llvm::TargetRegisterClass::getAllignment() will return the size and alignment of a virtual register used both in register allocation and stack slot assignment. llvm::TargetRegisterClass::alloc_order_begin() llvm::TargetRegisterClass::alloc_order_end() will give a list of the possible physical registers. When a virtual register is assigned a physical register

On 1/27/11 3:23 AM, Qingan Li wrote: > Hi, > > I wonder if there is an interface for me to access the type or size of > virtual registers in the SSA form? > I have scanned the MachineOperand in CodeGen part, and failed to find > this kind of info for virtual registers. The getType() method of Value * will return the LLVM type. The TargetData class will provide information on

On 4/3/07, David Greene <greened at obbligato.org> wrote: > > Toward a better register allocator, I'm attempting to understand > the dataflow information available to the allocator. > > What's the difference between LiveInterval information and LiveVariable > information? If a LiveInterval is based on a linear ordering of > the machine instructions, isn't it

Hi, I wonder if there is an interface for me to access the type or size of virtual registers in the SSA form? I have scanned the MachineOperand in CodeGen part, and failed to find this kind of info for virtual registers. -- Best regards, Li Qingan -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, Recently, I am working on some information collection on the machine instruction (MachineInstr) level. But, sometimes, I need check the corresponding IR level instruction of the a machine instruction. When visiting a machine instruction which is a call (MachineInstr::isCall()), I need to check the arguments of this call site. I know that the CallSite class provides good facility for this

Hi all, I'm tracking down a register allocation problem and I'm trying to understand this piece of code in InlineSpiller::spillAroundUses: // Find the slot index where this instruction reads and writes OldLI. // This is usually the def slot, except for tied early clobbers. SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); if (VNInfo *VNI =