similar to: [LLVMdev] LLVM API: how to determine if the register is the status register

Hello Vadim, > CMP modifies the status register (e.g. CPSR in ARM). The question is, are > there any modifications of the status register between those two compares. > In other words, how to know if CPSR is changed in the code after the first > CMP and before the second one. After register allocation all the machine instructions have flags on machine operands. So, in this particular

Hello everyone, I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two

On Tue, 16 Jun 2020 at 15:47, Tim Northover <t.p.northover at gmail.com> wrote: > > On Tue, 16 Jun 2020 at 10:23, Prathamesh Kulkarni via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > (b) Modifies RegisterCoalescer::reMaterializeTrivialDef and > > TargetInstrInfo::isReallyTriviallyReMaterializableGeneric to check > > for single live def, instead of

Hello, The function ARMBaseInstrInfo::AnalyzeBranch contains the following piece of code: } else if (I->isReturn()) { // Returns can't be analyzed, but we should run cleanup. CantAnalyze = !isPredicated(I); } else { This could lead to cases where for a block that ends with a conditional return, AnalyzeBranch returns false (i.e. analyzed), both TBB and FBB are

On Feb 17, 2011, at 10:35 PM, Вадим Марковцев wrote: > Hello everyone, > > I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". > Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Adding separate "s" instructions is

Doh. I missed the list in my first reply... Here's the replay of the conversation: ----- Renato: On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, > %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, >

Hello. I experience a problem when I try to run LLVM tests on the ARM "Beagle" board with Debian Lenny installed on it. When I execute "make check", I get the following output: llvm[0]: Running test suite make[1]: Entering directory `/mnt/markhor/llvm/nativeBuild/test' Making a new site.exp file... ( ulimit -t 600 ; ulimit -d 512000 ; ulimit -m 512000 ; ulimit -v 512000

Thank you for your reply! If liveness of APSR is not tracked, how does the code generator determine whether instructions like cmp are dead code or not? Is it true that, for every use of APSR (such as a conditional branch), the used def (such as cmp, add, etc.) is always in the same basic block? Is it true that APSR is never assumed to live across basic block boundaries? Thank you! Ming Zhang

Hi, I am missing atomic operations support for the ARM backend (see PR #3887) and started trying to implement them. Since this is the first time that I work on such stuff (and llvm) I am going to take the supposedly easy route and provide an implementation that will work on Linux systems. This involves calling a special function which the kernel handles itself. Details here:

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction has no results. It only alters the CPSR (current program

Hello everyone, I've added the "S" suffixed versions of ARM and Thumb2 instructions to the rest of those declared in tablegen. For example, "movs" or "muls". Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr r1, r2, r3 ----> orrs r1, r2, r3 cmp r1, 0 This optimization has

Hello everyone, I've added suffixed versions of ARM and Thumb2 instructions to tablegen. That is, for example, "movs" or "orrs". I implemented a rather simple codegen optimization which removes the comparison in patterns like orr r1, r2 ---> orrs r1, r2 cmp r1, 0 It works and have already shown nice acceleration (e.g., 3.3% in SQLite). I have a few

Hi, I have reworked my previous example and got something which is accepted by tblgen: let isCall = 1, Defs = [R0, R1, R2, R3, R12, LR, D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def ARM_ATOMIC_CMP_SWAP : ABXI<0b1011, (outs GPR:$dst), (ins i32imm:$ptr, i32imm:$old, i32imm:$new), "do_something", [(set GPR:$dst, (atomic_cmp_swap_32

On Thu, 9 Sep 2010 02:19:11 -0700 (PDT) markhor <markhor at ispras.ru> wrote: > > Hello. > > I experience a problem when I try to run LLVM tests on the ARM > "Beagle" board with Debian Lenny installed on it. I got this email 9 times at a difference of a few minutes, did you send it that many times, or something wrong with the mailing list? Best regards, --Edwin

You are trying to do a few different things here, and a uniform solution may not work for all of them. For a fixed instruction sequence, e.g. a special kind of move-and-branch sequence used for tail calls, you probably want a pseudo. If you are trying to combine arbitrary instructions together, e.g. Thumb IT blocks, you probably want to use bundles, even if the sequences are a fixed length. I

We weren''t taking the guest mode (CPSR) into account and would always access the user version of the registers. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- v2: Fix r8 vs r8_fiq thinko. --- xen/arch/arm/traps.c | 62 ++++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/vgic.c | 4 +- xen/arch/arm/vpl011.c | 4 +- xen/arch/arm/vtimer.c

Evan & llvmdev, I'm seeing a case where ARM Load/Store optimizer is breaking code. I have not had any luck trying to come up with a minimal example; it is breaking in our stage 2 LLVM build. But here's what I'm seeing in the debug output: # Before ARMLoadStoreOptimizer: BB#21: derived from LLVM BB %cond.end Live Ins: %LR %R0 %R1 %R7 %R10 %R11 Predecessors according to

I've committed a fix: r149970. Please try it. I would really appreciate it if you can provide us with a test case (unreduced test case is fine). Evan On 2012 2 4, at 09:46, David Meyer <pdox at google.com> wrote: > Evan & llvmdev, > > I'm seeing a case where ARM Load/Store optimizer is breaking code. I have not had any luck trying to come up with a minimal example;

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to