similar to: [LLVMdev] disable llc optimizations

On 12/6/10 11:39 AM, Andrew Lukefahr wrote: > Hi, > > How would I disable dead code elimination in llc? Can that be done > via the command line or do I need to modify llc's source? You can use llc --help-hidden to see a list of options. There are several -disable-xxx options that disable various code generator optimizations. That said, I, like Duncan, wasn't aware that

Ok, I'm trying to get llvm to decide when to turn the multiplier "on" and "off" for an ARM simulator. These instructions are just to let the simulator know when to power on/off the multiplier. I need to insert an instruction before the first multiply and another one after the last multiply in a basic block. I'm currently trying to figure out the best way to do that

On Dec 6, 2010, at 10:57 AM, John Criswell wrote: > On 12/6/10 11:39 AM, Andrew Lukefahr wrote: >> Hi, >> >> How would I disable dead code elimination in llc? Can that be done via the command line or do I need to modify llc's source? > > You can use llc --help-hidden to see a list of options. There are several -disable-xxx options that disable various code

I spent some time digging into a Valgrind report of uninitialized values in LLVM r287520 built using itself. (One of quite a few such reports that comes up during a "make check".) I could use another set of eyes on the issue if someone has time. This command gives me an error: valgrind -q ./bin/llc < /home/regehr/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll -march=hexagon

Just want to emphasize that on x86-64 and using Valgrind: LLVM compiled with LLVM gets 360 unexpected test fails LLVM compiled with GCC gets 22 unexpected test fails Of course I don't know how many of these are caused by this bitfield speculation issue. John On 11/21/2016 10:48 PM, regehr via llvm-dev wrote: > Alright, here's what seems to be happening... > > The testcase

Attached is my patch that adds a (debug build only) verifier pass and support for creating passes specified on the command line to llc. Let me know if it needs changes to be acceptable. One thing I noticed is that (eg.) opt and analyze have their options and globals in an anonymous namespace while llc doesn't. I just used llc's convention - which is preferable? As to testing - It works

On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote: > Ping. Anyone have any idea on how to fix this? Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); NonAllocatableRegs.flip();

Dale, Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions

I've recently sync'd to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything

On Apr 14, 2010, at 1:55 PMPDT, Villmow, Micah wrote: > I’ve recently sync’d to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc

On 7/26/05, Reid Spencer <reid at x10sys.com> wrote: > On Tue, 2005-07-26 at 17:25 -0700, Michael McCracken wrote: > > > Since I'm modifying llc, I have a couple small questions about that code: > > > > opt and analyze (and a couple of other places) add a verifier pass, > > but llc doesn't. > > This would seem to make sense for llc as well -

On Tue, 26 Jul 2005, Michael McCracken wrote: >> I can't see any harm in that. However, please make sure that it really >> isn't being run. The verifier can be hidden by various levels of >> abstraction. > > Assuming that I get everything with -debug-pass=Structure, then it isn't: -debug-pass=Structure does list everything. If you add it, please add it in an

Jakob, Here is my implementation of getAllocatableSet: BitVector AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF, const TargetRegisterClass *RC = NULL) const { BitVector Allocatable(getNumRegs()); Allocatable.clear(); return Allocatable; } Micah -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, May 03, 2010 9:52 AM To:

In llc's GetOutputStream we have this: raw_fd_ostream *FDOut = new raw_fd_ostream(OutputFilename.c_str(), /*Binary=*/true, Force, error); Why is Binary set true here? We don't know yet whether this is going to be an AsmFile or a MachOFile. Setting Binary=true causes the stream to be unbuffered. Is this what we want?

What guarantees, if any, does the scheduler make when two selection nodes are linked by a Flag type? Can I expect the machine instructions that are selected from the two nodes to be scheduled consecutively? I'm trying to implement code generation for SELECT_CC nodes in a back end that I'm working on. The compare operations on the architecture communicate via bits in a global status

I have a pass that modifies my machine dependent instructions and I have ran into a situation where I want to remove all instructions that an instruction is dependent on when I remove an instruction. Is there a way to do this using the API calls? For example, I have a sequence of instructions a = b + c d = c * c store d, *a load e, *a f = e + d since the store and load are

Hi, I have the following problem: In BB0 there is an instruction that defines a flag (implicit def) and in BB1 there is one that reads the flag (implicit use). When i run llc with -O3, the instruction in BB0 that defines the flag is removed. How can i prevent this? BB0 and BB1 are consecutive basic blocks. Thanks, Alex -------------- next part -------------- An HTML attachment was scrubbed...

On Tue, 2005-07-26 at 17:25 -0700, Michael McCracken wrote: > Since I'm modifying llc, I have a couple small questions about that code: > > opt and analyze (and a couple of other places) add a verifier pass, > but llc doesn't. > This would seem to make sense for llc as well - should I add it, with > the corresponding > hidden -no-verify option? I can't see any

On Jul 29, 2009, at 8:09 AM, David Greene wrote: > In llc's GetOutputStream we have this: > > raw_fd_ostream *FDOut = new raw_fd_ostream(OutputFilename.c_str(), > /*Binary=*/true, > Force, error); > > Why is Binary set true here? We don't know yet whether this is > going to be an > AsmFile or a MachOFile.

On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > On Mon, 2005-07-25 at 21:48 -0700, Michael McCracken wrote: > > On 7/25/05, Reid Spencer <reid at x10sys.com> wrote: > > > Why not just create your pass as a shared object and: > > > > > > opt -load mypass.so -mypass | llc > > > > My pass is an implementation of an analysis group that