similar to: [LLVMdev] [LLVMDev] The Basic Register allocator

I understand the mechanics. I don't know why a lesser weight is better than a greater weight. On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > >> I was studying the basic register allocator, and I am wondering why >> "LessSpillWeightPriority" priority was used over the

On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > I was studying the basic register allocator, and I am wondering why > "LessSpillWeightPriority" priority was used over the greater weight. Because the front of std::priority_queue is the largest element given the ordering.

Let me rephrase my question. The live intervals have a weight associated with them. What does this weight exactly represent? Thanks Jeff Kunkel On Thu, Oct 28, 2010 at 7:41 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I understand the mechanics. I don't know why a lesser weight is better > than a greater weight. > > > On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund

I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? - Thanks Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110120/fd429dbd/attachment.html>

On Sep 3, 2010, at 3:20 AM, Jeff Kunkel wrote: > Perhaps what I think is a problem really is not a problem. Yep. > The information I need is where the jumps occurs in the instructions vector. The machine instructions are already separated into basic blocks. http://en.wikipedia.org/wiki/Basic_block /jakob

I need to model my registers for my allocator. I need to identify the super-register and the sub-register conflicts. Something like: For each set of registers R in the set of aligned registers defined by the input request virtual register alpha. Now each register block r in R can have zero, one, or more registers defined in the block started at the aligned size and ending at the aligned size plus

I have noticed quite a few changes regarding register allocation. I am wondering will there be support for radically different data structures other than the LiveIntervals, Virtual Register Map, etc? I have build a custom data structure which has it's own intermediate representation like live-intervals, but much more conducive for my allocation algorithm. I do not know if LiveIntervals can

Thank you! The pieces are starting to fall into place finally. I need to track which MachineBasicBlocks branch into other MachineBasicBlocks. How do I do it? I see a MachineOperand can hold a MachineBasicBlock*. Does this mean the instruction may branch to the MachineBasicBlock, or can it be something like an object reference? - Thanks, Jeff Kunkel On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel

Would I be correct in assuming that the alias set is defined as the registers which may reside in the same space as the register? In other words the register is either a super or sub register which holds the same physical location in the register set? Could someone please explain what the Alias set is if it is not what I described above? TargetRegisterInfo::getAliasSet( unsigned reg ) Thanks

Jacob, have you completed the topological sorting or the registers? It seems I iterate through sub/alias-registers quite often, and I think a performance gain might occur if the sub-registers were grouped better. Thanks, Jeff Kunkel

On Jan 20, 2011, at 5:37 AM, Jeff Kunkel wrote: > I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? Not really, you have to use the use-def chain. See SplitAnalysis::analyzeUses(). /jakob -------------- next part -------------- A non-text

Bump: Does profiling / run time information exist when dealing with machine basic blocks? Thanks, Jeff Kunkel On Tue, Sep 28, 2010 at 9:51 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > How do I find the profiling or run time information for machine basic > blocks from a machine function? There are quite a few optimization > that may be preformed with this information, when it

I am looking for the slot index of a register around the given slot index Min. Is there a better way than the linear search: ... findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min ) ... for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg); mo; mo = mo->getNextOperandForReg() ) { SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() ); if(

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

On Oct 28, 2010, at 9:40 AM, Jeff Kunkel wrote: > I have noticed quite a few changes regarding register allocation. I am > wondering will there be support for radically different data > structures other than the LiveIntervals, Virtual Register Map, etc? Not any more than we already have. If anything, these data structures are going to be simplified. For instance, VirtRegMap's

I'm just running VS 10 in debug mode. In a step by step set up: 1. I download the svn 2. I make my changes 3. I compile the libraries 4. I make changes to the code within my project 5. I compile my code, and I re-link llc with my changed files. 6. I repeat 4,5, and 6 until it finally works. - Jeff Kunkel On Tue, Nov 2, 2010 at 1:21 PM, Óscar Fuentes <ofv at wanadoo.es> wrote: >

It is at the end allowing for oddities like debug info and multiple branches. You might want to look at AnalyzeBranch. On Sep 2, 2010, at 4:19 PMPDT, Jeff Kunkel wrote: > Is there any way to tell where in the Instruction list, the branch > to the other MachineBasicBlock happens? I know in the BasicBlock had > a nice api for it. > > Thanks, > Jeff Kunkel > > On Thu,

On Sep 29, 2010, at 8:11 AM, Jeff Kunkel wrote: > Jacob, have you completed the topological sorting or the registers? It > seems I iterate through sub/alias-registers quite often, and I think a > performance gain might occur if the sub-registers were grouped better. I abandoned the experiment because it didn't give a significant performance gain. Another problem is that aliases

How do I find the profiling or run time information for machine basic blocks from a machine function? There are quite a few optimization that may be preformed with this information, when it exists. Thanks, Jeff Kunkel

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is