similar to: [LLVMdev] the latency of opcode

On Nov 29, 2010, at 5:22 PM, huwei8717 wrote: > Hi, > > I have a llvm-pass in hand written by other people. There are following statements that I couldn't understand: > > -------------------------------program---------------------------------------------------- > ... > if (isa<CallInst>(inst) || isa<InvokeInst>(inst)) { > const CallSite cs(inst);

Hi, I have a llvm-pass in hand written by other people. There are following statements that I couldn't understand: -------------------------------program---------------------------------------------------- ... if (isa<CallInst>(inst) || isa<InvokeInst>(inst)) { const CallSite cs(inst); if (cs.getCalledFunction() == NULL) return dealAtIndirectCall(cs); else

tl;dr, I'd like to add my own instruction, but I'm running into problems due to my lack of x86 encoding/decoding understanding. Hello all. Currently, I'm working on adding my own x86 instruction. I have done this once before; the basic process I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into

----- Original Message ----- > From: "reed kotler" <rkotler at mips.com> > To: llvmdev at cs.uiuc.edu > Sent: Wednesday, February 13, 2013 6:00:45 PM > Subject: [LLVMdev] changing opcode > > Is there a simple way to just change the opcode of a machine > instruction. > > I have a lot of long/short pairs where when I know the offset, i can > replace

NVIDIA GPUs include a common scripting language (devinit) that can be interpreted by a number of "engines", e.g. within a kernel-mode software driver, the VGA BIOS or an on-board small microcontroller which provides certain security assertions (the 'PMU'). This system allows a GPU programming sequence to be shared by multiple entities that would not otherwise be able to execute

We've got both an sqrtf and an expf opcode in our architecture. If I call sqrt() on the C side, I see the sqrtf opcode show up in the generated assembly. However, if I call exp() on the C side, I don't see the expf opcode show up on the generated assembly, I see a call to an exp function from libm. Here's what we've got in our TargetInstrinfo.td file for both of these

Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],

Great info -- all of this has been incredibly useful. Do you have any links to the documentation from this, or does it just come from your experiential knowledge? FYI, I achieved what I set out to achieve when I wrote this email. I'm moving on to a more complex goal now, but the original question was answered completely, in my opinion. This was the key line: def CACHEOP : I<0x06, RawFrm,

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to

Is there a simple way to just change the opcode of a machine instruction. I have a lot of long/short pairs where when I know the offset, i can replace the long version with the short version. Tia. REed

hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in

Hello all, Is there an easy way to get the human-readable opcode mnemonic (e.g., "MOV32ri64", "CMP32ri8", "JLE_1") for a MachineInstr? I am writing a backend analysis pass for security research, where the idea is for a researcher to examine the output of my pass and identify instructions from it for use in an attack. Right now I'm representing unique

Hello, I m working towards backend. Here i need to define vector load and stores for 64 i32 elements. so in x86instrinfo.td i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))],

Hi, while testing syslinux-6.01_pre6 and syslinux-6.02_pre5 I noticed an illegal OpCode error on PXE exit. To reproduce: 1) Install syslinux-6.0x PXE environment 2) Use a config like I use (seems like this is getting triggered when the local boot menu entry will be executed) -> http://pastebin.com/raw.php?i=6tjqUAwX 3) Just let a client boot from network. It will hit timeout and the default

https://bugs.freedesktop.org/show_bug.cgi?id=57837 Priority: medium Bug ID: 57837 Assignee: nouveau at lists.freedesktop.org Summary: nouveau invalid opcode for NVIDIA QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: All Reporter: yetist at gmail.com Hardware:

_ Vbox 4.2.18 VM booted with FreeDOS floppy, kernel 2041, no config.sys, no autoexec.bat, no TSR's, no memory managers. _ The booting floppy includes syslinux.com 6.02. _ Two HDD images attached to the VM, MBR + 1 FAT16 formatted partition each. Executing syslinux.com -i c: (or "d:") results in the following error: "Invalid Opcode at AD04 5080 0206 5080 2021 3666 FFFD 0083

My first message didn''t get to the list, so I am trying once more. ---------- Forwarded message ---------- From: anatoly techtonik <techtonik@gmail.com> Date: Mon, Nov 14, 2011 at 5:46 PM Subject: Low memory corruption - trap invalid opcode ip:7f5c688028b0 sp:7ffff97af848 error:0 in ld-2.11.2.so[7f5c687ef000+1e000] To: xen-devel@lists.xensource.com I was redirected here from this

Hi to all, While trying to install syslinux on small (700 MB) FAT16 Partition on HP Server got Red Screen of Death with a register dump. Illegal OpCode EAX=00001F01 EBX=000001A4 ECX=00000000 EDX=00000019F EBP=0000FBFA ESI=000007BE EDI=00000800 DS=0000 ES=0000 FS=0000 GS=0000 CS:EIP=0000:000083A6 SS:ESP=1000:0000AFF6 EFLAGS=00000206 Tested many versions of syslinux: from 3.63 to 4.06:

Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've