Displaying 20 results from an estimated 8000 matches similar to: "[LLVMdev] [LLVMDev] Does LLVM have a random number generator?"
2010 Oct 09
0
[LLVMdev] [LLVMDev] Does LLVM have a random number generator?
I am plugging this into my code. If someone wants to take it out and
add it to the llvm library, it's a simple Linear Congruential
Generator, but here it is:
typedef struct random_number_gen {
unsigned a, c, seed, m;
random_number_gen( unsigned seed, unsigned modulo ) :
seed(seed), m(modulo) {
unsigned primes[] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 };
2010 Oct 09
0
[LLVMdev] [LLVMDev] Does LLVM have a random number generator?
I forgot to cc the list.
On Sat, Oct 9, 2010 at 10:47 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> On Sat, Oct 9, 2010 at 10:37 AM, Michael Spencer <bigcheesegs at gmail.com> wrote:
>>> On Sat, Oct 9, 2010 at 1:10 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
>>>> Hello, does LLVM already have a Random Number Generator built into
>>>>
2010 Nov 02
4
[LLVMdev] [LLVMDev] Long compile times
I'm just running VS 10 in debug mode. In a step by step set up:
1. I download the svn
2. I make my changes
3. I compile the libraries
4. I make changes to the code within my project
5. I compile my code, and I re-link llc with my changed files.
6. I repeat 4,5, and 6 until it finally works.
- Jeff Kunkel
On Tue, Nov 2, 2010 at 1:21 PM, Óscar Fuentes <ofv at wanadoo.es> wrote:
>
2010 Sep 28
2
[LLVMdev] [LLVMDev] Profiling information
How do I find the profiling or run time information for machine basic
blocks from a machine function? There are quite a few optimization
that may be preformed with this information, when it exists.
Thanks,
Jeff Kunkel
2011 Jan 20
4
[LLVMdev] [LLVMDev] Live Intervals and Finding the next usage
I have a live interval, and I would like to find out what SlotIndex the next
use the register will occur? Is there any way to map a live interval back
into instructions or SlotIndexes or blocks used by?
- Thanks
Jeff Kunkel
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2010 Oct 15
3
[LLVMdev] [LLVMDev] Trouble Linking
I ran cmake to build the visual studio projects. Then I included my
code under the Visual Studio interface, but I placed my code separate
from the CodeGen code. Visual studio was smart enough to compile and
link in my code into the CodeGen library. Thus, I did not need to add
my code into the same directory as the CodeGen files, and I did not
need to change the CMakeList.txt.
The offical name is
2010 Sep 29
0
[LLVMdev] [LLVMDev] Profiling information
Bump:
Does profiling / run time information exist when dealing with machine
basic blocks?
Thanks,
Jeff Kunkel
On Tue, Sep 28, 2010 at 9:51 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> How do I find the profiling or run time information for machine basic
> blocks from a machine function? There are quite a few optimization
> that may be preformed with this information, when it
2011 Jan 20
0
[LLVMdev] [LLVMDev] Live Intervals and Finding the next usage
I am looking for the slot index of a register around the given slot index
Min. Is there a better way than the linear search:
...
findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min )
...
for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg);
mo; mo = mo->getNextOperandForReg() )
{
SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() );
if(
2010 Nov 03
2
[LLVMdev] Static Profiling Algorithms in LLVM
You said it was expensive, but if you had to put a big-o estimate on it,
what would it be?
-Thanks
Jeff Kunkel
On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote:
> Hello Jeff,
>
> On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> > My god! I would love a branch predictor! It would simplify many aspects
> of
>
2007 Apr 24
5
Random Number Generator of Park and Miller
Hi,
I failed to search for R package providing random number generator of "Park
and Miller".
Anyone know any R package supporting this kind of function?
Thanks,
Grace
--
View this message in context: http://www.nabble.com/Random-Number-Generator-of-Park-and-Miller-tf3636501.html#a10154554
Sent from the R help mailing list archive at Nabble.com.
2010 Sep 02
5
[LLVMdev] [LLVMDev] [Modeling] About the structure of my allocator
I need to model my registers for my allocator. I need to identify the
super-register and the sub-register conflicts. Something like:
For each set of registers R in the set of aligned registers defined by the
input request virtual register alpha. Now each register block r in R can
have zero, one, or more registers defined in the block started at the
aligned size and ending at the aligned size plus
2010 Oct 15
2
[LLVMdev] [LLVMDev] Trouble Linking
- I placed my code in the the existing CodeGen library.
- No, it is not in the CMakeLists.txt. The code is separate from the
rest of the CodeGen code, but it is linked into the code gen library
automatically through the visual studio linker. Perhaps something
funny is going on here. I will try placing the code directly in the
library, and I will include it to the CMakeLists.txt.
- Thanks
- Jeff
2010 Nov 02
2
[LLVMdev] [LLVMDev] Long compile times
Hi, I am developing my register allocation algorithm in Visual Studio, and I
am hitting long compile times. I am wondering if there is a way to cut down
the time it takes for llc to link?
- Thanks
- Jeff Kunkel
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2010 Aug 31
3
[LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.
The method below takes in a register and returns a register. To me this
makes no sense because
when I already have a register, why would I need to get it? Could someone
please explain the
transformation that is happening here?
/// getRegister - Return the specified register in the class.
///
unsigned getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register
2010 Nov 02
0
[LLVMdev] [LLVMDev] Long compile times
Jeff Kunkel <jdkunk3 at gmail.com> writes:
> I'm just running VS 10 in debug mode. In a step by step set up:
>
> 1. I download the svn
> 2. I make my changes
> 3. I compile the libraries
> 4. I make changes to the code within my project
> 5. I compile my code, and I re-link llc with my changed files.
> 6. I repeat 4,5, and 6 until it finally works.
Well, that is
2010 Oct 11
1
[LLVMdev] Invoking LLVM front-end
I forgot to cc the list
On Mon, Oct 11, 2010 at 6:19 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> Well this is my 20,000 foot viewpoint of the project you have
> described. Also, I would appreciate if someone more knowledgeable
> revised my statements.
>
> First, I would make a mock machine with large register banks for each
> kind of operation and size combination. The
2010 Nov 03
0
[LLVMdev] Static Profiling Algorithms in LLVM
Hi Jeff,
There is an algorithm to build the dominator tree that is O(n2),
where n is the number of nodes on the control flow graph. I believe
exists another that is linear, but I don't which one of them is
implemented in LLVM.
The problem is that the branch predictor requires post dominance
information. None of the LLVM basic passes require post dominance
information (AFAIK), hence it is
2010 Oct 15
2
[LLVMdev] [LLVMDev] Trouble Linking
I'm sorry, I don't know what you were looking for. The first 5 were
scattered amidst different e-mails. The others have to do with
following what "RAFast" and "RALinScan" as examples. It's a linker
error, and I do not know why only opt and bugpoint does not compiler,
and why llc does not show my reg alloc pass anymore. It worked before
the API change e-mail was
2010 Oct 15
2
[LLVMdev] [LLVMDev] Trouble Linking
I am writing my register allocator directly in the LLVM tree, and I am
having trouble linking my project on windows msvc 10.0 compiler. The
error are below, but let me say what I have changed.
1. I added "(void) llvm::createJDKunkRegisterAllocator();" to the
struct ForcePassLinking::ForcePassLinking() method in
"llvm\include\llvm\LinkAllPasses.h"
2. I added "FunctionPass*
2008 Aug 14
2
[R] RNG Cycle and Duplication (PR#12540)
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I didn't describe the problem clearly. It's about the number of distinct=20
values. So just