Displaying 20 results from an estimated 30000 matches similar to: "[LLVMdev] Register aliases"
2010 Feb 22
5
[LLVMdev] Paired register allocation problem
Hi Anton,
Thanks for reply
> I have defined registers, aliases and subregister set.
> > The problem is that register allocator is using 32bit registers that are
> > already used in a pair, for example:
> > lw $r0, 16[$r12] // load word to r0
> > ld $p0, 36[$r12] // load doubleword to p0
> > shl $p0, $p0, $r0 // shift left p0 by r0 and store result in p0
2010 Feb 22
2
[LLVMdev] Paired register allocation problem
Hi All,
My target has 32bit registers, but it has some 64bit instructions which are
using pairs of these 32bit registers.
I have defined registers, aliases and subregister set.
The problem is that register allocator is using 32bit registers that are
already used in a pair, for example:
lw $r0, 16[$r12] // load word to r0
ld $p0, 36[$r12] // load doubleword to p0
shl $p0, $p0, $r0 // shift
2012 Mar 06
2
[LLVMdev] Assembly Mips from bitecode llvm
For compile and link Basicmath files (using shell script):
llvm-gcc -emit-llvm basicmath_small.c -c -o basicmath_small.bc
llvm-gcc -emit-llvm cubic.c -c -o cubic.bc
llvm-gcc -emit-llvm isqrt.c -c -o isqrt.bc
llvm-gcc -emit-llvm rad2deg.c -c -o rad2deg.bc
llvm-link basicmath_small.bc cubic.bc isqrt.bc rad2deg.bc -o basicmath.bc
2015 Mar 09
2
[LLVMdev] Out of tree targets
I believe we'd need LLVMBuild.txt even in autoconf build - for bunch
of autogenerated stuff, e.g. list of all asmprinters / asmparsers /
InitializeAllTargetInfos, etc., since targets are not autoregistered
anymore.
On Mon, Mar 9, 2015 at 7:20 PM, Eric Christopher <echristo at gmail.com> wrote:
> Hi Neil,
>
> Weird, I'd think the cmake build should probably do something
2011 Jan 30
2
[LLVMdev] question on assembler for systemz backend
What assembler are people using with the SystemZ backend?
I am trying to assemble the output of the SystemZ backend with the GNU
binutils assembler (build with --target=s390x-linux). I get errors when
assembling instructions with literals that are negatives. For example,
the test case test/CodeGen/SystemZ/01-RetImm.ll gives errors:
$ s390x-as 01-RetImm.s
01-RetImm.s: Assembler messages:
2011 Jan 30
2
[LLVMdev] question on assembler for systemz backend
Hi Anton,
On 01/30/2011 12:44 PM, Anton Korobeynikov wrote:
> Hello
>
>> I am trying to assemble the output of the SystemZ backend with the GNU
>> binutils assembler (build with --target=s390x-linux). I get errors when
>> assembling instructions with literals that are negatives. For example,
>> the test case test/CodeGen/SystemZ/01-RetImm.ll gives errors:
>
2011 May 01
2
[LLVMdev] LoopInfo are not able to identify some natural loops?
Thanks for the reply. The LoopInfo pass can actually identify the loop I
mentioned. My former question is due to a bug in my pass. What I worried is
that LoopInfo can not identify all the natural loops for the benchmarks I
use, but now I haven't found any such cases.
Bo
On Sun, May 1, 2011 at 4:24 PM, John Criswell <criswell at illinois.edu> wrote:
> On 4/30/11 8:52 AM, Bo Wu
2012 Mar 06
0
[LLVMdev] Assembly Mips from bitecode llvm
Ok. And what does llvm-gcc --version show?
---
With best regards,
Anton Korobeynikov
On Mar 6, 2012 5:22 PM, "Rafael Parizi" <parizi.computacao at gmail.com> wrote:
>
> For compile and link Basicmath files (using shell script):
>
> llvm-gcc -emit-llvm basicmath_small.c -c -o basicmath_small.bc
> llvm-gcc -emit-llvm cubic.c -c -o cubic.bc
> llvm-gcc -emit-llvm
2013 Apr 14
2
[LLVMdev] [RFC/PATCH][0/4] New SystemZ backend
Hello,
I'd like to propose the addition of a new SystemZ backend to the LLVM and
Clang code base. We're interested in this for the same reason we've been
interested in the PowerPC back-end recently: to enable packages in upcoming
enterprise Linux distributions that need LLVM support (e.g. 3D desktop
support via llvmpipe).
Now, I understand that a SystemZ backend used to be part of
2013 Sep 24
2
[LLVMdev] request for tutorial
On 24 September 2013 03:00, Sean Silva <chisophugis at gmail.com> wrote:
> http://llvm.org/devmtg/2009-10/Korobeynikov_BackendTutorial.pdf
>
He did this again last year at the EuroLLVM:
http://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf
They're similar, but different. I assume the newer one is better, but you
can look at both, shouldn't take too long.
2010 Aug 11
1
[LLVMdev] Unnecessary Win64 stack allocations...
I'm trying to understand the Win64 case of the code below, from X86RegisterInfo.cpp:
// If this is x86-64 and the Red Zone is not disabled, if we are a leaf
// function, and use up to 128 bytes of stack space, don't have a frame
// pointer, calls, or dynamic alloca then we do not need to adjust the
// stack pointer (we fit in the Red Zone).
if (Is64Bit &&
2006 May 24
5
Joining variables
Hello,
If I have two variables that are factors or characters and I want to
create a new variable that is the combination of both what function can
I use to accomplish this?
Ex.
Var1 Var2
SA100055113 19851113
And I want
NewVar
SA10005511319851113
Thanks in advance.
Cameron Guenther, Ph.D.
Associate Research Scientist
FWC/FWRI, Marine Fisheries Research
100 8th Avenue S.E.
St.
2011 Jan 30
1
[LLVMdev] question on assembler for systemz backend
On 01/30/2011 02:09 PM, Anton Korobeynikov wrote:
>> I'd still like to know if anyone has sucessfully assembled SystemZ generated
>> assembly language with a binutils assembler, and if so, how.
> Almost all testsuite passed ~ 1.5 years ago (with clang + gas). I
> doubt anyone tried to assembler anything else after that time.
>
Lots of things have changed in 1.5 years with
2010 Jan 30
3
[LLVMdev] [patch] MicroBlaze Backend
> Your patch looks very clean. Some comments:
Heh, Jakob was faster :)
> - I think you have some literal tabs in your instruction descriptions.
The tabs can be seen in some other places as well. Also, there is a
"mix" of coding conventions in the files. It will be really nice to
use only one :)
> - Your tests are nice, but you could use some more of them. I would recommend
2006 May 16
3
subset
Hello everyone,
I have a large dataset (x) with some rows that have duplicate variables
that I would like to remove. I find which rows are the duplicates with
X1<-which(duplicated(x)). That gives me the rows with duplicated
variables. Now, how can I remove just those rose from the original data
frame. I think I can create a new data frame without the duplicates
using subset. I have tried:
2006 Nov 28
5
Counting zeros in a matrix
Hi All,
If you could help me with this problem I would greatly appreciate it.
Suppose I have a matrix A:
1 1 1 1 0 1 1 1 1
1 1 1 0 1 0 1 0 0
1 0 1 0 0 1 0 0 0
1 1 0 0 0 0 1 0 0
I would like, for each row, to sum the number of times a 0 appears in
front of a 1. So what I would like is to have
Sum
1 1 1 1 0 1 1 1 1 1
1 1 1 0 1 0 1 0 0 2
1 0 1 0 0 1 0 0 0 2
1 1 0 0 0 0 1
2006 Oct 19
2
randomize a matrix
Hello everyone,
If I have an incidence matrix of 0 and 1's
P=[1 1 1 1 1 1
1 1 1 1 0 0
1 1 1 0 0 0
1 1 1 0 0 0
1 1 0 0 0 0]
I want to create a new uniform random matrix [a] that is filled with 0's
and 1's but constrained so that the row and column sums are the same as
in [P]. Does anyone know how to accomplish this?
Thanks in advance
Cameron Guenther, Ph.D.
2005 Nov 21
3
Warning message help
I am trying to great a new column of effort data from an existing vector
of gears used.
It is a simple code where
effort[Gear==300]=(DIST_TOW*7412)
effort[Gear==301]=(DIST_TOW*7412)
The code appears to work for some of the data but fails for others and
inserts a NA value
I also get this warning message
Warning message:
number of items to replace is not a multiple of replacement length
Can
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In