Displaying 20 results from an estimated 7000 matches similar to: "[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers."
2010 Sep 03
2
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
It's not too much of a problem then. I can make a DenseMap between the
registers and my registers. It's just one more intermediate step for a
lookup.
I wish to mimic all the of the registers on the machine with
my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register
is used I can assign it easily. I know about alias register and those are
taken care of ever so
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
TargetRegisterInfo::getNumRegs().
Generally, it's best not to make any assumptions about the internal ordering or numbering if you can avoid it. What are you looking to do?
-Jim
On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote:
> How do I get the total number of machine registers? I have currently a MachineFunction and some derivatives.
>
> How are the machine registers ordered
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
On Sep 3, 2010, at 10:46 AM, Jeff Kunkel wrote:
> It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup.
>
> I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I
2010 Sep 03
0
[LLVMdev] [LLVMDev] [Question] How do I get the number of machine registers.
On Sep 3, 2010, at 9:37 AM, Jeff Kunkel wrote:
> How do I get the total number of machine registers? I have currently a MachineFunction and some derivatives.
>
> How are the machine registers ordered internally? Can I index them off of a zero based array or do I have to create a map to have them be zero based?
Registers are numbered from 1 to TRI::getNumRegs()-1. Reg 0 is not a
2009 Dec 09
5
[LLVMdev] [PATCH] increase the max number of physical registers
On Dec 8, 2009, at 3:31 PM, Jakob Stoklund Olesen wrote:
>
> On Dec 8, 2009, at 11:33 AM, Evan Cheng wrote:
>
>> This caused a massive slow down to post-ra scheduler (llc -O3 on x86, -O2 on ARM). I'm going to revert it for now until it has been addressed.
>
> Probably caused by this member:
>
> /// KillIndices - The index of the most recent kill (proceding
2010 Jul 06
1
[LLVMdev] [PATCH] increase the max number of physical registers
Hello,
This patch was reverted and the revert was forgotten to be undone
after the performance regression it introduced was fixed.
Can someone please revert it back (i.e. increase the max physreg size
to 16K or even better to 32K) to enable us to experiment with large
register number machines again? :)
It was this trivial patch:
Index: include/llvm/Target/TargetRegisterInfo.h
2010 Aug 31
3
[LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.
The method below takes in a register and returns a register. To me this
makes no sense because
when I already have a register, why would I need to get it? Could someone
please explain the
transformation that is happening here?
/// getRegister - Return the specified register in the class.
///
unsigned getRegister(unsigned i) const {
assert(i < getNumRegs() && "Register
2009 Dec 08
2
[LLVMdev] [PATCH] increase the max number of physical registers
This caused a massive slow down to post-ra scheduler (llc -O3 on x86, -O2 on ARM). I'm going to revert it for now until it has been addressed.
Evan
On Dec 7, 2009, at 11:39 AM, Dan Gohman wrote:
>
> On Dec 7, 2009, at 11:15 AM, Pekka Jääskeläinen wrote:
>
>> Here's the actual patch, sorry ;)
>
> Applied in r90789.
>
> Dan
>
>
>
2011 Jan 29
1
[LLVMdev] The type or size of virtual registers
llvm::TargetRegisterClass::getSize()
llvm::TargetRegisterClass::getAllignment()
will return the size and alignment of a virtual register used both in
register allocation and stack slot assignment.
llvm::TargetRegisterClass::alloc_order_begin()
llvm::TargetRegisterClass::alloc_order_end()
will give a list of the possible physical registers.
When a virtual register is assigned a physical register
2010 May 03
2
[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions
On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote:
> Ping. Anyone have any idea on how to fix this?
Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work:
BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
NonAllocatableRegs.flip();
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 3:53 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"vivek pandya" <vivekvpandya at gmail.com>
> *To: *"Quentin Colombet" <qcolombet at apple.com>
> *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" <llvm-dev at lists.llvm.org>,
>
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 8:44 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ------------------------------
>
> *From: *"vivek pandya" <vivekvpandya at gmail.com>
> *To: *"Hal Finkel" <hfinkel at anl.gov>
> *Cc: *"llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" <
> matze at braunis.de>, "Mehdi
2016 May 25
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
>
>
> On Wed, May 25, 2016 at 10:08 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote:
>
>> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at gmail.com>> wrote:
>>
>> Dear
2010 Oct 07
2
[LLVMdev] [LLVMDev] Has anyone written this?
It would go something like like the code below. The goal would be to
turn the basic blocks which the graph looks like "...->x->y->..."
where the instructions of x and y could live in the same basic block
without a jump or fall through in between.
bool runOnMachineFunction(MachineFunction &mf) {
BitVector seen( mf.size() );
for( unsigned i = 0, e = mf.size();
2011 Sep 06
3
[LLVMdev] bug in TableGen when generating RegisterInfo?
Hi everyone,
I found some peculiar behavior of TableGen when generating
[TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in
this file, leading to a compilation error. I think this is because in
RegisterInfoEmitter.cpp, RegisterAliases are declared as "std::map<Record*,
std::set<Record*>, LessRecord>"
and a requirement for std::map is that the
2009 Dec 08
0
[LLVMdev] [PATCH] increase the max number of physical registers
On Dec 8, 2009, at 11:33 AM, Evan Cheng wrote:
> This caused a massive slow down to post-ra scheduler (llc -O3 on x86, -O2 on ARM). I'm going to revert it for now until it has been addressed.
Probably caused by this member:
/// KillIndices - The index of the most recent kill (proceding bottom-up),
/// or ~0u if the register is not live.
unsigned
2010 Sep 01
0
[LLVMdev] [LLVMDev] [Question] The TargetRegisterClass has a confusing method.
Aye, I understand it's an index into an array, but what is the difference
between the index i and the return value.
Do I have to worry that register values from a TargetRegisterClass could be
either zero based or some other base? Are there other methods that rely on
zero based in the TargetRegisterClass?
I thought register values were "global," but this transformation makes a
2010 Oct 15
1
[LLVMdev] how to get MachineBasicBlock of a BasicBlock
Also note: there may be multiple MachineBasicBlock's for a single
BasicBlock.
- David M
On Fri, Oct 15, 2010 at 4:59 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> I don't think you can.
>
> The BasicBlock is a member of MachineBasicBlock. It is not inherited,
> so it cannot be cast. The number of the MachineBasicBlock is not the
> same as any BasicBlock values.
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
>
> Dear Mentors,
>
> Please help me to understand our plan to implement Interprocedural Register allocator by propogating register usage info. While writing this mail I am considering all previous discussion over llvm-dev and IRC.
>
> 1) A MachineFunction pass to be executed POST-RA to
2010 Oct 15
2
[LLVMdev] how to get MachineBasicBlock of a BasicBlock
Hello, we can get BasicBlock from MachineBasicBlock through MachineBasicBlock::getBasicBlock() function, but how can I get MachineBasicBlock of a BasicBlock?
Thank you!