similar to: [LLVMdev] [LLVMDev] [Fishing expedition] Virtual Machines and LLVM

I'm just running VS 10 in debug mode. In a step by step set up: 1. I download the svn 2. I make my changes 3. I compile the libraries 4. I make changes to the code within my project 5. I compile my code, and I re-link llc with my changed files. 6. I repeat 4,5, and 6 until it finally works. - Jeff Kunkel On Tue, Nov 2, 2010 at 1:21 PM, Óscar Fuentes <ofv at wanadoo.es> wrote: >

Bump: Does profiling / run time information exist when dealing with machine basic blocks? Thanks, Jeff Kunkel On Tue, Sep 28, 2010 at 9:51 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > How do I find the profiling or run time information for machine basic > blocks from a machine function? There are quite a few optimization > that may be preformed with this information, when it

I am looking for the slot index of a register around the given slot index Min. Is there a better way than the linear search: ... findDefUsesAroundIndex( LiveInterval* li, SlotIndex Min ) ... for( MachineOperand * mo = MRI->getRegUseDefListHead(li->reg); mo; mo = mo->getNextOperandForReg() ) { SlotIndex si = SI->getInstructionIndex( use.getOperand().getParent() ); if(

How do I find the profiling or run time information for machine basic blocks from a machine function? There are quite a few optimization that may be preformed with this information, when it exists. Thanks, Jeff Kunkel

I have a live interval, and I would like to find out what SlotIndex the next use the register will occur? Is there any way to map a live interval back into instructions or SlotIndexes or blocks used by? - Thanks Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110120/fd429dbd/attachment.html>

Hello, does LLVM already have a Random Number Generator built into it's library somewhere? I know code generation is suppose to be deterministic, but when producing a random number can be deterministic if the random number generator is also deterministic. - Thanks - Jeff Kunkel

I ran cmake to build the visual studio projects. Then I included my code under the Visual Studio interface, but I placed my code separate from the CodeGen code. Visual studio was smart enough to compile and link in my code into the CodeGen library. Thus, I did not need to add my code into the same directory as the CodeGen files, and I did not need to change the CMakeList.txt. The offical name is

You said it was expensive, but if you had to put a big-o estimate on it, what would it be? -Thanks Jeff Kunkel On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Jeff, > > On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > > My god! I would love a branch predictor! It would simplify many aspects > of >

- I placed my code in the the existing CodeGen library. - No, it is not in the CMakeLists.txt. The code is separate from the rest of the CodeGen code, but it is linked into the code gen library automatically through the visual studio linker. Perhaps something funny is going on here. I will try placing the code directly in the library, and I will include it to the CMakeLists.txt. - Thanks - Jeff

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is

I need to model my registers for my allocator. I need to identify the super-register and the sub-register conflicts. Something like: For each set of registers R in the set of aligned registers defined by the input request virtual register alpha. Now each register block r in R can have zero, one, or more registers defined in the block started at the aligned size and ending at the aligned size plus

Hi, I am developing my register allocation algorithm in Visual Studio, and I am hitting long compile times. I am wondering if there is a way to cut down the time it takes for llc to link? - Thanks - Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20101102/c0c7a2bc/attachment.html>

I am plugging this into my code. If someone wants to take it out and add it to the llvm library, it's a simple Linear Congruential Generator, but here it is: typedef struct random_number_gen { unsigned a, c, seed, m; random_number_gen( unsigned seed, unsigned modulo ) : seed(seed), m(modulo) { unsigned primes[] = { 2, 3, 5, 7, 11, 13, 17, 19, 23, 29 };

I forgot to cc the list On Mon, Oct 11, 2010 at 6:19 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > Well this is my 20,000 foot viewpoint of the project you have > described. Also, I would appreciate if someone more knowledgeable > revised my statements. > > First, I would make a mock machine with large register banks for each > kind of operation and size combination. The

Also note: there may be multiple MachineBasicBlock's for a single BasicBlock. - David M On Fri, Oct 15, 2010 at 4:59 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I don't think you can. > > The BasicBlock is a member of MachineBasicBlock. It is not inherited, > so it cannot be cast. The number of the MachineBasicBlock is not the > same as any BasicBlock values.

Jeff Kunkel <jdkunk3 at gmail.com> writes: > I'm just running VS 10 in debug mode. In a step by step set up: > > 1. I download the svn > 2. I make my changes > 3. I compile the libraries > 4. I make changes to the code within my project > 5. I compile my code, and I re-link llc with my changed files. > 6. I repeat 4,5, and 6 until it finally works. Well, that is

It would go something like like the code below. The goal would be to turn the basic blocks which the graph looks like "...->x->y->..." where the instructions of x and y could live in the same basic block without a jump or fall through in between. bool runOnMachineFunction(MachineFunction &mf) { BitVector seen( mf.size() ); for( unsigned i = 0, e = mf.size();

I am writing my register allocator directly in the LLVM tree, and I am having trouble linking my project on windows msvc 10.0 compiler. The error are below, but let me say what I have changed. 1. I added "(void) llvm::createJDKunkRegisterAllocator();" to the struct ForcePassLinking::ForcePassLinking() method in "llvm\include\llvm\LinkAllPasses.h" 2. I added "FunctionPass*

Spiller::Spill( LiveInterval *li, SmallVectorImpl<LiveInterval*> &newIntervals, const SmallVectorImpl<LiveInterval*> &spillIs ); has two reference vectors which contain a small list of Live Intervals. What is the register allocator's job to do with these intervals other than analysis. What more needed other than to know

I understand the mechanics. I don't know why a lesser weight is better than a greater weight. On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > >> I was studying the basic register allocator, and I am wondering why >> "LessSpillWeightPriority" priority was used over the