similar to: [LLVMdev] [LLVMDev] May Physical Registers be given to the register allocator?

I understand the mechanics. I don't know why a lesser weight is better than a greater weight. On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > >> I was studying the basic register allocator, and I am wondering why >> "LessSpillWeightPriority" priority was used over the

Let me rephrase my question. The live intervals have a weight associated with them. What does this weight exactly represent? Thanks Jeff Kunkel On Thu, Oct 28, 2010 at 7:41 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > I understand the mechanics. I don't know why a lesser weight is better > than a greater weight. > > > On Thu, Oct 28, 2010 at 7:22 PM, Jakob Stoklund

I need to model my registers for my allocator. I need to identify the super-register and the sub-register conflicts. Something like: For each set of registers R in the set of aligned registers defined by the input request virtual register alpha. Now each register block r in R can have zero, one, or more registers defined in the block started at the aligned size and ending at the aligned size plus

Upon writing my register allocation algorithm, I am concerned that a load may be skipped due to a branch. For instance consider the psudocode int x = 1 ... if( false ) load x y = 3*x else y = 4*x ... The load happens in the false block because this is when the variable is first seen. The load is not preformed in the else block because the register allocator may see it loaded already. Do

It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I know about alias register and those are taken care of ever so

Perhaps what I think is a problem really is not a problem. So when a jump occurs from one block A to block B, then the registers are certain state, and register allocation happens with the initial state defined by A->B. When a third block C jumps to block B, the state of the registers are different. Thus register allocation needs to account for the jump from C->B, by a few ways: 1. The

I was studying the basic register allocator, and I am wondering why "LessSpillWeightPriority" priority was used over the greater weight. - Thanks Jeff Kunkel

It is at the end allowing for oddities like debug info and multiple branches. You might want to look at AnalyzeBranch. On Sep 2, 2010, at 4:19 PMPDT, Jeff Kunkel wrote: > Is there any way to tell where in the Instruction list, the branch > to the other MachineBasicBlock happens? I know in the BasicBlock had > a nice api for it. > > Thanks, > Jeff Kunkel > > On Thu,

Thank you! The pieces are starting to fall into place finally. I need to track which MachineBasicBlocks branch into other MachineBasicBlocks. How do I do it? I see a MachineOperand can hold a MachineBasicBlock*. Does this mean the instruction may branch to the MachineBasicBlock, or can it be something like an object reference? - Thanks, Jeff Kunkel On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel

Would I be correct in assuming that the alias set is defined as the registers which may reside in the same space as the register? In other words the register is either a super or sub register which holds the same physical location in the register set? Could someone please explain what the Alias set is if it is not what I described above? TargetRegisterInfo::getAliasSet( unsigned reg ) Thanks

On Sep 3, 2010, at 10:46 AM, Jeff Kunkel wrote: > It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. > > I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I

On Oct 28, 2010, at 4:05 PM, Jeff Kunkel wrote: > I was studying the basic register allocator, and I am wondering why > "LessSpillWeightPriority" priority was used over the greater weight. Because the front of std::priority_queue is the largest element given the ordering.

Hi Jeff, There is an algorithm to build the dominator tree that is O(n2), where n is the number of nodes on the control flow graph. I believe exists another that is linear, but I don't which one of them is implemented in LLVM. The problem is that the branch predictor requires post dominance information. None of the LLVM basic passes require post dominance information (AFAIK), hence it is

How do I get the total number of machine registers? I have currently a MachineFunction and some derivatives. How are the machine registers ordered internally? Can I index them off of a zero based array or do I have to create a map to have them be zero based? Thanks, Jeff Kunkel -------------- next part -------------- An HTML attachment was scrubbed... URL:

You said it was expensive, but if you had to put a big-o estimate on it, what would it be? -Thanks Jeff Kunkel On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Jeff, > > On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > > My god! I would love a branch predictor! It would simplify many aspects > of >

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

Jeff Kunkel <jdkunk3 at gmail.com> writes: > I am writing my register allocator directly in the LLVM tree, and I am > having trouble linking my project on windows msvc 10.0 compiler. The > error are below, but let me say what I have changed. > 1. I added "(void) llvm::createJDKunkRegisterAllocator();" to the > struct ForcePassLinking::ForcePassLinking() method in

Hello, does LLVM already have a Random Number Generator built into it's library somewhere? I know code generation is suppose to be deterministic, but when producing a random number can be deterministic if the random number generator is also deterministic. - Thanks - Jeff Kunkel

- I placed my code in the the existing CodeGen library. - No, it is not in the CMakeLists.txt. The code is separate from the rest of the CodeGen code, but it is linked into the code gen library automatically through the visual studio linker. Perhaps something funny is going on here. I will try placing the code directly in the library, and I will include it to the CMakeLists.txt. - Thanks - Jeff

I am writing my register allocator directly in the LLVM tree, and I am having trouble linking my project on windows msvc 10.0 compiler. The error are below, but let me say what I have changed. 1. I added "(void) llvm::createJDKunkRegisterAllocator();" to the struct ForcePassLinking::ForcePassLinking() method in "llvm\include\llvm\LinkAllPasses.h" 2. I added "FunctionPass*