Displaying 20 results from an estimated 800 matches similar to: "[LLVMdev] Rendering MachineFunctions as HTML."
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2009 Jun 16
3
[LLVMdev] x86 Intel Syntax and MASM 9.x
I would like to use the LLVM x86 code generator to emit Intel syntax
that is compatible with Microsoft's MASM 9.x. Taking the TOT LLVM, from
last week, I have found a number of changes that are required to make
this work, most of which are straight forward but a couple I wanted to
check with the group to see what people thought was the best thing to
do. In particular, I have made all necessary
2015 Mar 24
3
[LLVMdev] [PATCH] fix outs/ins of MOV16mr instruction (X86)
Hi,
This patch fixes outs/ins of MOV16mr instruction of X86.
Thanks.
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index e9a0431..f5b2064 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in {
def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Sun, 1 Oct 2006, Roman Levenstein wrote:
> I'm trying to implement a new backend for an embedded CISC processor.
> Therefore I thought that it makes sense to take X86 target as a basis,
> to save some time.
Ok. Note that the X86 backend is one of the most complex though, because
it supports several subtargets and ABIs, which makes it more complex than
some other targets.
>
2002 May 15
3
Struchture change of a data frame
Hi guys
I've got an easy question but couldn't find any quick solution. I woulk
like to change the following matrix
good bad worse
Blue 1 2 2
Yellow 2 1 3
Black 3 4 4
Into the following structure
good 1 Blue
Bad 2 Blue
Worse 2 Blue
Good 2 Yellow
Bad 1 Yellow
Worse 2 Yellow
Good 2 Black
Bad 4 Black
Worse 4 Black
Thanks a lot.
Regards
Beat Huggler
---
Beat Huggler
Quantitative
2011 May 26
0
[LLVMdev] x86 SSE4.2 CRC32 intrinsics renamed
FYI,
The CRC64 intrinsics were renamed to CRC32 since there is no such thing. See below for details.
Chad
On May 26, 2011, at 4:13 PM, Chad Rosier wrote:
> Author: mcrosier
> Date: Thu May 26 18:13:19 2011
> New Revision: 132163
>
> URL: http://llvm.org/viewvc/llvm-project?rev=132163&view=rev
> Log:
> Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
Hi Chris,
Thanks a lot for your answer!
Chris Lattner wrote:
>> 1. Why does X86 instruction set description provide different
>> descriptions for the same instructions, which differ only in the
size
>> of operands?
>> E.g.
>>
>> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
>> "mov{b} {$src, $dst|$dst, $src}",
2011 Apr 17
2
2.0.12 ipwd.c does not compile under solaris
the new src/lib/ipwd.c introduced in 2.0.12 no longer compiles on
solaris. Under solaris,
the *_r routines doesn't pass in result as the last parameter and return
errno - it just returns result.
obviously a job for configure.....
--
Roger Fujii<rmf at lookhere.com>
2019 Mar 25
2
Overlapping register groups in old 8-bit MC6809 processor.
Hi
I'm returning to my MC6809 back-end from a health-related hiatus. The assembler is tantalisingly close, but I've got some parsing and matching problems.
The register set; these overlap in annoying ways, for instance, two instructions TFR and EXG each have a single opcode, and the post-byte specifies which registers are to be involved, but the registers can be 8- or 16-bit, and 2 of
2007 Aug 09
5
Unremovable file in ZFS filesystem.
I managed to create a link in a ZFS directory that I can''t remove. Session as follows:
# ls
bayes.lock.router.3981 bayes_journal user_prefs
# ls -li bayes.lock.router.3981
bayes.lock.router.3981: No such file or directory
# ls
bayes.lock.router.3981 bayes_journal user_prefs
# /usr/sbin/unlink bayes.lock.router.3981
unlink: No such file or directory
# find . -print
2003 Apr 01
1
Nlminb equivalent function in R?
Hello everybody
I need some help. Currently, I'm translating a code from Splus to R. In Splus code there is the function nlminb (Nonlinear Minimization subject to Box Constraints) used. Does anybody know an equivalent function in R?
Thanks for help
Kind regards,
Beat Huggler
_____________________________________________
Beat Huggler
Quantitative Analysis
RMF Investment Management
2009 Jan 24
2
IO: streaming input data
Hello -
I need to read in some tables that are embedded within data files like this:
line 1
line 2
data table
01000
10110
00011
end table
line 3
line 4
Is there any way to read just the data by telling an input device to start
reading when it encounters the keyword "data table" and stop reading at "end
table"?
Thanks in advance,
Jesse
--
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2010 Nov 08
2
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
Hi, while writing my register allocator, I have come across a case which
confuses me because the llvm definition cannot be mapped to machine code.
For instance I come across (1) and I reduce it to (2). However a copy
instruction cannot move from EDX to CX. What mechanics in LLVM will tell me
that I cannot make this move during register allocation, or how can I tell
from (1) that I cannot execute
2010 Jul 26
1
[LLVMdev] How to specify patterns for instructions with accumulator in selection DAG?
Hi,
I am wondering how to specify the selection DAG patterns for instructions
that use accumulator.
For example multiply-accumulate instruction with one destination operand and
two source operands:
mac $dst, $src1, $src2 ;; $dst += $src1*$src2
Seems that it has a cycle in the pattern. So how do I specify it in the DAG?
There are a few instructions in the ARM backend like this one, but the
2001 Mar 05
0
Portable openssh-2.5.1p1, auth-passwd.c, yellow pages, expire field
Hi,
I'm having trouble with auth_password() failing on my linux box using
yellow pages. I've tracked the problem down to the following:
pw_password = "RMf.YivanoZc2,o01N"
encrypted_password = "RMf.YivanoZc2"
This fails on the return(strcmp(encrypted_password, pw_password) == 0).
because crypt() only returns 13 characters. I seem to remember the
2002 Mar 21
0
RODBC
Hi guys
I'm working with with R1.4.1 on windows
I'm trying to import data from the ODBC (Access database) with the
library RODBC. Every thing works perfect except that the dates are
factors.
> library(RODBC)
> xx <- odbcConnect("grave_liv")
> dat <- sqlQuery(xx,"SELECT All_MONTHLY.ID, All_MONTHLY.Date,
All_MONTHLY.RoR FROM (Reasons INNER JOIN
2004 Sep 15
6
Bessel function
Dear all
Currently, I'm implementing the generalized hyperbolic distribution into
Splus. Unfortunately the Bessel function is not implemented in Splus. In
R the Bessel function does exist but it is an internal function and I'm
not able to look at the code.
Is there any possibility to see the code of the Bessel function in R or
does anybody has an implementation of the Bessel function in
2010 Nov 08
0
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
On Nov 8, 2010, at 12:04 PM, Jeff Kunkel wrote:
> Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code.
>
> For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during
2002 Feb 06
1
Probblems with loading the tcltk library
Hi guys
Recently a wanted to look at the opotunities which are suported by the
labrary of tcltk. Unfortunatly I couldn't load the library and it
occured the following error message:
Error in firstlib(which.lib.loc, package) :
TCL_LIBRARY is not set
Error in library(pkg, character.only = TRUE) :
.First.lib failed
I've tried to load it in sveral ways. I reinstalt the
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Mon, 2 Oct 2006, Roman Levenstein wrote:
>>> Wouldn't it be possible and even more clean to have just one
>>> description like (I use a pseudo-description here):
>>>
>>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst,
>>> (i8mem|i16mem|i32mem):$src),
>>> "mov{b} {$src, $dst|$dst, $src}", []>,