Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Handling of IMPLICIT_DEF in llvm 2.7"
2009 Jun 04
1
[LLVMdev] assertion in LeakDetector
Hi Bill,
I am using the following version of BuildMI :
MachineInstrBuilder BuildMI(MachineFunction &MF,
const TargetInstrDesc &TID,
unsigned DestReg)
I do the following :
void createInstrs(std::vector<MachineInstr *>& ilist)
{
Machine Instr *mi;
mi = BuildMI(MF, someTID, somereg);
2009 Jun 04
0
[LLVMdev] assertion in LeakDetector
On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote:
> I am seeing the following assertion in leak detector.
>
> /llvm/lib/VMCore/LeakDetector.cpp:43:
> void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T =
> void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"'
> failed.
>
> I am
2009 Jul 10
0
[LLVMdev] MCInst
On Jul 9, 2009, at 5:34 PM, David Greene wrote:
> Can someone explain what MCInst is vs. MachineIntr?
Sure. MCInst is designed to be part of the "MC" set of libraries,
which is stuff dealing with machine code. We're building a suite of
assemblers and disassemblers out of this.
MCInst is integral to this plan. For an assembler you have two pieces:
1. "Recognize"
2009 Jun 04
2
[LLVMdev] assertion in LeakDetector
I am seeing the following assertion in leak detector.
/llvm/lib/VMCore/LeakDetector.cpp:43:
void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T =
void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"'
failed.
I am creating a list of instructions using BuildMI() and adding them
to a basic block using BB->insert(). I am seeing this
2012 Feb 28
0
[LLVMdev] Getting corresponding c-instruction line number along with ir-instruction in a function's CFG
Hi
I am not a good programmer but for my project i have to use llvm to generate CFG for c programs where i have a mapping from IR instruction in CFG to their respective c instruction. After surfing a in source of llvm i did the following change in printInstruction() function in llvm/lib/VMCore/AsmWriter.cpp file. .....void AssemblyWriter::printInstruction(const Instruction &I) { if
2010 Aug 04
1
[LLVMdev] JITing code with indirect branch in LLVM 2.7
I am trying to JIT some code containing an indirect branch (and the
corresponding store i8* blockaddress(@label)). I am using LLVM 2.7
code base. I build the ExecutionEngine using EngineBuilder, and call
engine->getPointerToFunction(func). When I use
setOptLevel(llvm::CodeGenOpt::None), the JITing fails with the
following message :
JIT.h:131: virtual void*
2009 Jun 03
0
[LLVMdev] Adding instructions to MachineBlock
On Wed, Jun 3, 2009 at 12:46 PM, Manjunath Kudlur<keveman at gmail.com> wrote:
> Hello,
>
> I am writing a MachineFunction pass that converts vector instructions
> to a sequence of scalar instructions.
Why? That really isn't the level you want to be doing that sort of
thing normally. Usually, legalization turns illegal vector operations
into legal scalar operations.
-Eli
2009 Jun 03
2
[LLVMdev] Adding instructions to MachineBlock
Hello,
I am writing a MachineFunction pass that converts vector instructions
to a sequence of scalar instructions. First, I go through the function
and look for vector registers. For each vector register, I create a
set of corresponding scalar registers using createVirtualRegister()
function and put it in a map. Then I go through the function and
replace vector instructions.The basic structure of
2009 Jul 10
1
[LLVMdev] MCInst
On Friday 10 July 2009 00:19, Chris Lattner wrote:
> asmprinter::printInstruction will lower a MachineInstr to an MCInst,
> then call the MCInst asmprinter to do the hard formatting work. You
> can see a horrible simple skeleton of this idea in
> X86ATTAsmPrinter::printMachineInstruction.
Yep, that's where I hit the problem. I'm patching the sources for the
comment emitter
2012 May 14
1
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
I used llvm-stress to find a similar problem on x86-64. See http://llvm.org/bugs/show_bug.cgi?id=12821.
BTW, llvm-stress is a great tool!
/Patrik Hägglund
________________________________
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jakob Stoklund Olesen
Sent: den 9 maj 2012 18:21
To: Jonas Paulsson
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev]
2012 May 09
0
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
On May 9, 2012, at 6:27 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote:
> Hi,
>
> Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
>
> %vreg9<def> = IMPLICIT_DEF
> %vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
> %vreg12<def> = sub %vreg10<kill>,
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
Hi,
I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
2012 May 09
2
[LLVMdev] register allocation problems in trunk with IMPLICIT_DEF
Hi,
Recently code using IMPLICIT_DEF and INSERT_SUBREG started to break:
%vreg9<def> = IMPLICIT_DEF
%vreg10<def> = INSERT_SUBREG %vreg9<kill>, %vreg1<kill>, hi
%vreg12<def> = sub %vreg10<kill>, %vreg11<kill>
=>
%vreg10<def> = IMPLICIT_DEF
%vreg10:hi<def> = COPY %vreg1<kill>
2009 May 08
0
[LLVMdev] Question on tablegen
Manjunath,
I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov.
For example,
Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask.
So I have dst, src0, src1, imm1, imm2
And I have my asm look similar to:
Add dst, src0.imm1, src1.imm2 and then in the asm
2011 Apr 07
1
[LLVMdev] IMPLICIT_DEF?
Hi,
I have a MachineInstr that writes to a subreg, but clobbers the superreg.
How should I BuildMI this instruction?
I try to do a
IMPLICIT_DEF super_reg
and then write to a subreg of that super register
, but it gets DCE:ed.
Is there a way to express this clobbering of a superregister?
thanks,
Jonas
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2009 Jun 08
2
[LLVMdev] Tablegen question
Christian,
Thanks for your reply and the wiki entry. I did search the archives,
but evidently I didn't search for the right thing. My bad. Anyways, I
am still wondering about the other part of my question. Why aren't
there Tablegen backends specific to some architecture backends? Let me
describe a different scenario. Suppose my architecture has vector and
scalar units, and suppose I want
2009 May 08
2
[LLVMdev] Question on tablegen
Dan,
Thanks a lot. Using a modifier in the assembly string works for this
case. I am trying to solve a related problem. I am trying to print out
a set of "mov" ops for the vector_shuffle node. Since the source of
the "mov" is from one of the sources to vector_shuffle, depending on
the mask, I am not sure what assembly string to emit. For example, if
I have
d <-
2008 Mar 04
0
[LLVMdev] Deleting Instructions after Intrinsic Creation
Hi,
I tried creating intrinsics which
are to be placeholders for a set of instructions which
should not be executed by the backend.
I want to retain only intrinsic,phi and terminator instructions in a basic
block.
I have taken care of the external dependencies of basic block.
How do I delete the rest of the instructions?
Thank You
Aditya
P.S:
2018 Apr 12
0
How to specify the RegisterClass of an IMPLICIT_DEF?
On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote:
>
> But there is one small issue in the inference of RegisterClass of the
> implicitly defined register.
>
> As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass.
>
> This register class accepts the v2f32 type, but for others addressing
> mode context this register should be
2007 Aug 10
2
[LLVMdev] Extending AsmPrinter
I'm looking at extending AsmPrinter to pretty-print comments after
instructions (I'm adding the necessary fields to MachineInstr to do this).
I'm trying to grok AsmWriterEmitter and having a tough go of it. I look at
X86GenAsmWriter1.inc (the Intel syntax writer) and understand that
there's a case block for printing operands under several switch statements,
one per