Displaying 20 results from an estimated 100 matches similar to: "[LLVMdev] MC: Object file specific parsing"
2018 Sep 28
3
error: expected memory with 32-bit signed offset
Hi,
I want to encode Loongson ISA initially
https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac
gslbx $2,0($3,$4)
It is equivalent to:
dadd $1, $3, $4
lb $2,0($1)
I just use mem_simmptr as the default value of DAGOperand MO ,
because MipsMemAsmOperand use parseMemOperand to parse general
MemOffset and only *one* AnyRegister , for example:
0($1)
But
2015 Nov 26
2
Accessing TableGen defined variable in the cpp code
Hello all,
I would like to assign some bits in the instructions, based on the order of
mnemonics that appear in a special order. I can do it in TableGen itself,
but it will not be well maintainable based on the things I want to
accomplish.
Therefor, I would like to do it in the c++ file which is waaay easier (at
least in the concept!!).
Imagine I have this in my base class in TableGen:
2015 Sep 28
2
Parse Instruction
Hi all,
in most of the architectures, assembly operands are comma-separated.
I would like to parse an assembly code that is space-separated and I am
having a bit of problem.
In *ParseInstruction* function, I don't know what is the easiest way to
figure out how many operands a mnemonic expected to have.
In comma-separated assembly code, it just consuming commas (while
2015 Sep 28
3
Parse Instruction
Hi ES,
From what I understand instruction parsing is divided into two parts:
- Parsing an operand list (XXXAsmParser::ParseInstruction)
- Turning the operand list into an actual instruction
(XXXAsmParser::MatchAndEmitInstruction)
The second part does the validation (e.g. how many operands, what kind,
etc) while the first part only does the parsing. That's why I think in
the first part
2012 Feb 17
0
Passing a value to js.erb
Rails 3.1.3
I''m trying to pass a value to ''save.js.erb'' .
in the view, I have put
<%= hidden_field_tag "video-id", @video.id, { :id => "video-id" } %>
then, I can retrieve it by
var idval = $(''#video-id'').val();
It certainly gets the value.
The problem is then I need to pass it to the following.
I tried,
2012 May 09
1
[LLVMdev] Directive parsing for AsmParser
I'm trying to build a standalone assembler for Mips using AsmParser and I'm facing a problem with assembly directives. Mips assembler has following syntax for .set directive
.set reorder
or
.set noreorder
which allow/disallow assembler to change the order of instructions in the block that follows. As the implemented AsmParser requires .set directive to have the following syntax:
2010 May 05
0
[LLVMdev] Is the option --enable-shared discontinued in 2.7?
Jeffrey Yasskin wrote:
>> Would you try the patch at
>> http://codereview.appspot.com/download/issue968046_1.diff? It should
>> make the BSDs fall into the same path as Linux, and since you use gnu
>> ld, that should work for you.
>>
>
> Ping?
>
Sorry for the delay.
Here is what I am getting after applying the patch:
gmake[2]: Leaving directory
2013 Nov 12
2
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi David,
Thanks for your efforts here. I have a few comments on your patch, although
I realise it's still a work in progress.
+class ConstantPool {
+ MCSymbol *Label;
+ typedef std::vector<const MCExpr*> EntryVecTy;
Use a SmallVector here?
+ MCSymbol *getLabel() {return Label;}
+ size_t getNumEntries() {return Entries.size();}
+ const MCExpr *getEntry(size_t Num) {return
2013 Nov 12
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi Amara,
Thanks for your suggestions. I have made the changes you suggested and added
a new test to check that we print an error when parsing a non-ldr mnemonic
with an operand containing `=`. The updated patch is attached.
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation
> -----Original Message-----
> From: Amara Emerson
2010 Feb 17
1
[LLVMdev] Kaleidoscope toy4 failure seg fault on llvm::ExecutionEngine::getTargetData (this=0x0)
On Wed, Feb 17, 2010 at 6:29 AM, Conrado Miranda
<miranda.conrado at gmail.com> wrote:
> First, you have to call llvm-g++ to use the llvm-gcc front end, but it
> doesn't matter here.
I got the compile command from the Kaleidoscope documentation.
> I'd like to suggest that you use pastebin to put your code and the send us
> the link, so that we can download it. The
2010 May 05
2
[LLVMdev] Is the option --enable-shared discontinued in 2.7?
On Tue, May 4, 2010 at 5:31 PM, Yuri <yuri at tsoft.com> wrote:
> Jeffrey Yasskin wrote:
>>>
>>> Would you try the patch at
>>> http://codereview.appspot.com/download/issue968046_1.diff? It should
>>> make the BSDs fall into the same path as Linux, and since you use gnu
>>> ld, that should work for you.
>>>
>>
>> Ping?
2010 Feb 17
0
[LLVMdev] Kaleidoscope toy4 failure seg fault on llvm::ExecutionEngine::getTargetData (this=0x0)
First, you have to call llvm-g++ to use the llvm-gcc front end, but it
doesn't matter here.
I'd like to suggest that you use pastebin to put your code and the send us
the link, so that we can download it. The problem is that TheExecutionEngine
is set to NULL (maybe because of a previous error), but it will be really
better if you use pastebin.
On Wed, Feb 17, 2010 at 6:01 AM, Todd Rovito
2010 Feb 17
2
[LLVMdev] Kaleidoscope toy4 failure seg fault on llvm::ExecutionEngine::getTargetData (this=0x0)
I am new to llvm so I might be missing a critical step. My system is
Fedora 12 but this also happens in Mac OS X 10.6.2. Here are the
steps I used to compile llvm:
export TARGETS=x86,x86_64,cpp
export INSTALLDIR=/home/rovitotv/llvm
../llvm-2.6/configure --prefix=$INSTALLDIR --enable-bindings=none
--enable-targets=$TARGETS --enable-optimized
--with-llvmgccdir=$INSTALLDIR
2013 Nov 16
2
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Moving discussion to llvm-commits now that I have a more developed
implementation:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20131111/195401.
html
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
> Behalf Of David Peixotto
> Sent: Tuesday, November 12, 2013 11:09 AM
> To: 'Amara Emerson'
>
2013 Dec 17
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi David,
Maybe I’m just blind, but where’s the code to handle the .ltorg directive? Is that a separate patch, maybe? Without that, this is not going to be usable in any circumstance using subsections-via-symbols.
+typedef std::map<const MCSection *, ConstantPool> ConstantPoolMapTy;
This feels odd to me. Can you elaborate a bit more on the data structure choices?? I would have expected
2010 Apr 03
0
[LLVMdev] ARM AsmLexer
The attached patch implements simple target-specific AsmLexers for ARM and Thumb. They are shallow subclasses of a common tokenizer that uses a std::map of register names to IDs to recognize register names, and reports those as AsmToken::Register tokens instead of identifiers.
I intend to use the ARM and Thumb AsmLexers as part of an extension of the EnhancedDisassembly library, which provides
2012 May 23
0
[LLVMdev] Assembly macros instantiation problem
Hello,
I've noticed a following strange behavior:
clang-3.2 fails to compile/parse any assembly code that invokes macros which named arguments contains non alphanumeric characters.
For example, compilation of the following code snippet would fail with "Parameter not found" error:
.macro mov_macro reg_1, reg_2
movl %\reg_1, %\reg_2
.endm
mov_macro eax, ebx
Although, if one
2011 Jul 06
1
[LLVMdev] clang-llvm exceptions problem powerpc-apple-darwin
I am getting assembler errors on clang-llvm-2.9 output for a program
with
exceptions that I do not get when using the installed g++
Mac OS-X 10.4 powerpc-apple-darwin
> as -version
Apple Computer, Inc. version cctools-590.23.2.obj~17, GNU assembler
version 1.38
the folks at gnu-binutils assure me this is an assembler bug, but
also that this isn't
a recognizable "gnu"
2012 Oct 17
0
[LLVMdev] Hexagon Assembly parser question
On Oct 17, 2012, at 3:29 PM, David Young <davidy at codeaurora.org> wrote:
> Hi,
> I’m trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward.
>
> But….
> Hexagon assembly does not follow the “Mnemonic Rx Rx …” format that is expected by the assembly parsing infrastructure,
2012 Oct 17
3
[LLVMdev] Hexagon Assembly parser question
Hi,
I'm trying to enable the hexagon LLVM assembly parser. It seem like there
is a lot of work that has been done to make this parsing straightforward.
But..
Hexagon assembly does not follow the "Mnemonic Rx Rx ." format that is
expected by the assembly parsing infrastructure, represented by:
StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
This