similar to: [LLVMdev] Reducing the size of LLVM and clang

Displaying 20 results from an estimated 50000 matches similar to: "[LLVMdev] Reducing the size of LLVM and clang"

2009 Dec 08
2
[LLVMdev] Back-end with general purpose registers
Hi all, I am trying to write a back-end for LLVM where any instruction may take any type of data. I am looking for the output to be of the format: inst.type reg1,reg2 etc. Where inst is the instruction, e.g. mov and type is data-type e.g. f32 etc. I tried creating a back-end with a register class which could take i32 and f32: def GPRegs : RegisterClass <"Test",
2010 Jun 15
0
[LLVMdev] [cfe-dev] Reducing the size of LLVM and clang
Is that really going to make a significant difference? I've been looking at the same issue, in my case trying to make a simple JIT (using only LLVM at the time, not trying to use clang to parse and then JIT, but rather deserializing bytecode and JIT it). I made the simplest example I could based on my limited knowledge of the interfaces, and even linking with -dead_strip and optimizing for
2011 Mar 10
0
[LLVMdev] Detrimental optimization for reducing relocations.
> So, clearly the optimization is making things worse. Would it be okay to delete > this code and eliminate the isBaseAddressKnownZero? I would like to get rid of > it. I think it is OK. I can see ld/gdb expecting a relocation, but if that is the case we should just have a flag saying it is needed. If you are really motivated to check it, run the gdb testsuite with your patch, but on
2011 Mar 10
3
[LLVMdev] Detrimental optimization for reducing relocations.
I was looking into the AsmPrinter and the method EmitSectionOffset which contains this code: -------------------------------------------------------------------------------- // If the section in question will end up with an address of 0 anyway, we can // just emit an absolute reference to save a relocation. if (Section.isBaseAddressKnownZero()) { OutStreamer.EmitSymbolValue(Label, 4,
2011 Mar 10
2
[LLVMdev] Detrimental optimization for reducing relocations.
----- Original Message ---- > From: Rafael Ávila de Espíndola <rafael.espindola at gmail.com> > To: llvmdev at cs.uiuc.edu > Sent: Thu, March 10, 2011 4:22:32 PM > Subject: Re: [LLVMdev] Detrimental optimization for reducing relocations. > > > So, clearly the optimization is making things worse. Would it be okay to >delete > > this code and eliminate the
2003 Nov 20
2
What is vuid?
I'm getting the following errors in my error logs: ERROR! vuid 100 did not map to a valid vuser struct! At the time this error was being created I was trying to add a domain user as a local admin. I was trying to get the browse list of domain users up, but being denied. Cheers Jeff -- Jeff Gardiner [ gardiner@nospam.imaging.robarts.ca ] System Administrator - Imaging Research
2011 Mar 11
0
[LLVMdev] Detrimental optimization for reducing relocations.
> Will the testsuite work on ELF? The patch does not make any functional change > for the other formats. I know that gdb is okay with the example, but that > doesn't say very much. The patch is probably OK then. The gdb testsuite works with clang on ELF. There used to be a lot of silly failures like it not expecting clang warnings, but I think most of the current ones are real.
2013 Oct 01
2
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi all, I'm working on llvm assembler support for Mips and for a while I'm trying to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in
2011 Jan 05
2
OT: Reducing pdf file size
Greetings Does anyone have any suggestions for reducing pdf file size, particularly pdfs containing photos, without sacrificing quality? Thanks for any tips in advance. Cheers Kurt *************************************************************** Kurt Lewis Helf, Ph.D. Ecologist EEO Counselor National Park Service Cumberland Piedmont Network P.O. Box 8 Mammoth Cave, KY 42259 Ph: 270-758-2163
2013 Oct 02
0
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi Vladimir, ARM does similar things for complex assembly pseudos. Have a look at the definition and use of AsmPseudoInst in the ARM backend. They’re not typically expanding to multiple “real” instructions, but that’s an implementation detail, not a constraint. -Jim On Oct 1, 2013, at 5:36 AM, Vladimir Medic <Vladimir.Medic at imgtec.com> wrote: > Hi all, > I'm working on llvm
2013 Oct 02
1
[LLVMdev] [TableGen][AsmParser][MC] isAsmParserOnly flag in class Instruction
Hi Jim, I did look at the ARMAsmParser and it seems to me that it is using a switch/case construct to change the opcode and the operands, but this construct may become too large eventually. I was wondering if it is possible to use isAsmParser only flag to call dedicated methods, like dedicated parsers for AsmOperands. Regards Vladimir ________________________________ From: Jim Grosbach [grosbach
2015 Oct 02
2
buildbot failure in LLVM on clang-cmake-mips
Thanks. From the debugging I've done so far it looks like it could be another 32-bit big-endian specific bug. It seems to be segfaulting in the memset() in allocate_stack.c (from glib) because given stack pointer is null. I'm guessing this is because it read the wrong half of a 64-bit value somewhere but I haven't identified where it goes wrong. ________________________________________
2015 Oct 01
2
buildbot failure in LLVM on clang-cmake-mips
On Thu, Oct 1, 2015 at 12:08 PM, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: > I do. I'll take a look. > > Is there a way for owners to get emails for long-lasting failures? > I'm not sure what the generic setup is, but at least for the builder/slave I admin, it emails me on every failure. So I get a lot of mail, continuously, if there's a consistent
2015 Oct 02
3
buildbot failure in LLVM on clang-cmake-mips
I've just noticed that this is a new test added in r248325 and has never passed on this builder. Added the author of the test (Evgeniy). From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Daniel Sanders via llvm-dev Sent: 01 October 2015 20:34 To: David Blaikie Cc: llvm-dev Subject: Re: [llvm-dev] buildbot failure in LLVM on clang-cmake-mips > > I do. I'll take
2016 Feb 16
2
[Firefox] How to compile firefox with Clang for Linux
Hi All, I am trying to build firefox with clang in Ubuntu 14.04 64bit. There is always configure failed errors problem. I follow compiling firefox with clang on linux <https://developer.mozilla.org/en-US/docs/Compiling_Firefox_With_Clang_On_Linux>. I add "export CC=clang export CXX=clang++" to mozconfig file. I wonder whether you guys have built firefox with clang in Linux. Could
2014 Nov 24
4
[LLVMdev] Proposed patches for Clang 3.5.1
Hi, I'd like to propose the following patches for inclusion in Clang 3.5.1. Proposed clang patches: * r213769 - Fix test/Driver/cl-x86-flags.c by providing explicit -target * r214025 - [Driver][Mips] Check output of -dynamic-linker arguments by the Clang driver * r214662 - [Mips] Add the `mips64-linux-gnu` target to the test case to check `in128` type handling. *
2016 Mar 31
3
DNS issues after FSMO seize
Aaaaaaand more problems... Welcome to the continuing saga of FILER. It appears that neither SOA or NS records were updated during the process of moving fsmo roles to CBADC01. SOA entries on all three active DCs point to FILER. There aren't any NS records for any of the new DCs, only FILER. In RSAT each DNS server's properties show filer.cb.cliffbells.com is the primary server. This
2011 Sep 07
3
[LLVMdev] Proposal: floating point accuracy metadata (OpenCL related)
Hi, This is my proposal to add floating point accuracy support to LLVM. The intention is that the frontend may provide metadata to signal to the backend that it may select a less accurate (i.e. more efficient) instruction to perform a given operation. This is primarily a requirement of OpenCL, which specifies that certain floating point operations may be computed inaccurately. Comments
2011 Sep 08
1
[LLVMdev] [cfe-dev] Proposal: floating point accuracy metadata (OpenCL related)
Hi Peter, This sounds like I really good idea. One thing that did occur to me though from an OpenCL point of view is that ULP accuracy requirements can differ for embedded and full profile so that may need to be handled somehow. Thanks, Rob On Wed, 2011-09-07 at 21:55 +0100, Peter Collingbourne wrote: > Hi, > > This is my proposal to add floating point accuracy support to LLVM. >
2018 Jan 07
0
Reducing code size of Position Independent Executables (PIE) by shrinking the size of dynamic relocations section
* Roland McGrath: > Given this corpus of "reloc traces" you can code up many competing encoding > formats and do serious measurements of their space savings across the > entire corpus from simple simulations without having to implement each > encoding in an actual toolchain and dynamic linker to do the analysis. On the other hand, the linker currently assumes that the order