similar to: [LLVMdev] How to handle predicate registers which can also work inverted way.

2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: >> >> Hi, >> >> I was wondering if LLVM supports predicates and conditional execution. >> Something like we have in IA64. >> There is a register class of predicates and then every instruction may >> be

On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > Hi, > > I was wondering if LLVM supports predicates and conditional execution. > Something like we have in IA64. > There is a register class of predicates and then every instruction may > be predicated by a register from this class. > For example: > > cmp_less p, x, y // p is a predicate

On Tue, May 24, 2011 at 8:35 AM, roy rosen <roy.1rosen at gmail.com> wrote: > 2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > >> > >> Hi, > >> > >> I was wondering if LLVM supports predicates and conditional execution. > >>

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add instruction Is there support in LLVM to something

Hi, >> The problem is that the existing integer arithmetic operations on i8 >> are not legal to be executed on the predicate registers (i.e., clang >> would generate an i8 expression for the addition of two char >> variables.) Hexagon cannot do integer arithmetic operations using the >> predicate registers. so what can you actually do with predicate registers?

Salut Sebastian! On 01/06/2012 18:19, Sebastian Pop wrote: > Salut Ivan, > > On Fri, Jun 1, 2012 at 7:22 AM, Ivan Llopard<ivanllopard at gmail.com> wrote: >> Hi Sebastian, >> >> Le 25/05/2012 18:54, Sebastian Pop a écrit : >>> On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop<spop at codeaurora.org> wrote: >>>> On Thu, May 24, 2012 at

Salut Ivan, On Fri, Jun 1, 2012 at 7:22 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi Sebastian, > > Le 25/05/2012 18:54, Sebastian Pop a écrit : >> On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop<spop at codeaurora.org>  wrote: >>> On Thu, May 24, 2012 at 5:06 PM, Hal Finkel<hfinkel at anl.gov>  wrote: >>>> Sebastian,

Hi, I am planning to generate code for a peculiar architecture with _no_ branch instructions (!), but with predicated loads and stores to memory. This means the architecture is not Turing complete, is going to waste a lot of computation, and any input program that can hope to get compiled for this architecture must have loops that can be fully unrolled, and all its functions must get fully

Hi Marcello, I am sure I've seen some postings on the list concerning architectures that support predicated execution and how to map that to LLVM IR, I'm just not sure anymore when and who was involved :). I have implemented your first suggestion for targets that do not have predicated instructions (where control flow to data flow conversion with explicit maintaining of masks and

On Oct 7, 2007, at 12:51 AM, Nikhil A. Patil wrote: > Hi, > > I am planning to generate code for a peculiar architecture with > _no_ branch instructions (!), but with predicated loads and stores > to memory. This means the architecture is not Turing complete, is > going to waste a lot of computation, and any input program that can > hope to get compiled for this

On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement > branching on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so > I'm not exactly sure on what is the

Salut Duncan, On Sun, Jun 3, 2012 at 7:55 AM, Duncan Sands <baldrick at free.fr> wrote: > Hi, > >>> The problem is that the existing integer arithmetic operations on i8 >>> are not legal to be executed on the predicate registers (i.e., clang >>> would generate an i8 expression for the addition of two char >>> variables.)  Hexagon cannot do integer

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that they are 8 bits.  The reason for this is

On Fri, Jul 14, 2017 at 10:54 AM, Daniel Berlin <dberlin at dberlin.org> wrote: > > >> I think you're done when you get everything that you have that fits into >> a model of local transformations and that should be run to a fixed point. >> > > Sure, but to point out what you certainly already know, that's almost > every optimization you can think of

On Sun, Jun 3, 2012 at 7:11 AM, Ivan Llopard <ivanllopard at gmail.com> wrote: >> So the solution that I was investigating looks like this: >> >>      for (unsigned int i = 0; i<  ISD::BUILTIN_OP_END; ++i) { >>        switch (i) { >>        // By default all operations on i8 have to be promoted to i32. >>        default: >>        

Hi Eli, On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> Hey folks, >> >> We are having some difficulty with how we have been representing our >> predicate registers, and wanted some advice from the list.  First, we >> had been

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this

Hi, On Tue, May 22, 2012 at 11:35 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi Ivan, > > On Tue, May 22, 2012 at 5:09 PM, Ivan Llopard <ivanllopard at gmail.com> wrote: >> Hi Sebastian, >> >> On 22/05/2012 23:25, Sebastian Pop wrote: >>> So my question is how do we specify that for most of the operations i8 >>> should be promoted