similar to: [LLVMdev] [PATCH] a few minor documentation corrections

Hi, *make install* works for me on Ubuntu. Does the output of *make install* show that it was successful? Was it setup to be installed in a PATH location of Fedora? --John -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110411/8bab1522/attachment.html>

Hi, Sorry, but I cant seem to repeat the issue anymore. 'make install' works fine now. I have no idea what went wrong the first time. Thanks for the effort, and sorry to have bothered you with this. On Mon, Apr 11, 2011 at 2:25 PM, John Myers <atomicdog.jwm at gmail.com> wrote: > Hi, > > make install works for me on Ubuntu. > Does the output of make install show

John Myers <atomicdog.jwm at gmail.com> writes: > I'm looking for some pointers on how to troubleshoot this problem. I'm > trying to write a backend for the AVR. > There is an undefined reference at line 48 which is the line FrameInfo() is > on. I've tried to use the MSP430 and other targets as references so I'm not > sure > what changes I did would cause a

Hi, I'm looking for some pointers on how to troubleshoot this problem. I'm trying to write a backend for the AVR. There is an undefined reference at line 48 which is the line FrameInfo() is on. I've tried to use the MSP430 and other targets as references so I'm not sure what changes I did would cause a problem on this line? AVRTargetMachine::AVRTargetMachine(const Target &T,

I'm having a great deal of trouble figuring out how to write instruction patterns which actually match the DAG produced by the compiler. I can't seem to find any documentation on both what the various nodes represent or on what the syntax accepted by TableGen is. The backends I have access to all seem to do this in different (and obscure) ways. And when things go wrong the compiler seems

Hi, I am new to LLVM and I find TableGen language really cryptic. The reference manual to the language is not helpful either. I can look at the existing .td file and reverse engineer but I am looking for a detailed manual. Specifically, I have below questions: 1. What is a basic syntax for writing a dag? From the lang ref manual I can see that its something like operator followed by ArgList which

On Mon, Feb 14, 2011 at 10:39 AM, Talin <viridia at gmail.com> wrote > > >> I'd like to wait until I get some feedback - I don't know yet if anyone is > having trouble building or running the thing... > Hi Talin, This is the build error I get on my ubuntu 64 bit system... john at ubuntu:~/src/build-llbrowse$ make [ 5%] Building CXX object

Hi, I just compiled llvm/clang from source on my fedora linux system as specified on the website, but running 'make' and 'make install' does not seem to result in a 'functioning' installation ? I mean, neither 'clang' or 'scan-build' seem to be found ? Are there any other actions I need to perform on my linux system in order to complete the installation

Hi, What is the Cmake equivalent to configures target option [ ./configure --target=avr-atmel-none] ? --John -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120710/5405f54b/attachment.html>

Possible to add a test case? Micah > -----Original Message----- > From: Sebastian Pop [mailto:spop at codeaurora.org] > Sent: Wednesday, June 20, 2012 1:40 PM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu > Subject: Re: [LLVMdev] How to define macros in a tablegen file? > > On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at

On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Possible to add a test case? I am not really sure what I would check. At first, I thought to add a testcase to test/TableGen; as this patch does not modify tablegen, it doesn't make sense. What kind of test should I write for this? The test should be a tablegen file that includes

On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote: > For reference, here is how the SPU port is using code and pattern fragments: > > // Holder of code fragments (you'd think this'd already be in > // a td file somewhere... :-) And this comment makes me think, shouldn't this class CodeFrag be included in the same place where PatFrag is

The language I'm targeting doesn't have flags; I'd like to implement ADDE as a macro or psuedo-instruction that takes 3 parameters and returns 2. In my InstrInfo.td file, tablegen complains if I try to define multiple return values; adde is defined in TargetSelectionDAG.td to be a binary op that takes an extra flag in and sends an extra flag out. I tried to custom lower ADDE

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> wrote: > Try visualising the DAG like this. > > ``` > ---- GPR:$rA > / > set GPR:$rd ---- add > \ > ---- GPR:$rB > ``` > > Each instruction forms a DAG with its operands being subnodes. > >

I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also,

Hi, I was wondering if someone could explain precisely what the ComplexPattern tablegen class does? Here's the first line of the definition (from TargetSelectionDAG.td) for reference: class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = [], list<SDNodeProperty> props = [],

On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at codeaurora.org> wrote: > On Wed, Jun 20, 2012 at 12:26 PM, Sebastian Pop <spop at codeaurora.org> wrote: >> For reference, here is how the SPU port is using code and pattern fragments: >> >> // Holder of code fragments (you'd think this'd already be in >> // a td file somewhere... :-) > >

Hi Heikki, > just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] > > gives me error that extloav2i8 is not defined. I don't have a target to test this on, but looking at include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" PatFrag, at least. I'd suggest a pattern along the lines of: (set V2I32Regs:$result, (v2i32 (sextloadvi8

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like