similar to: [LLVMdev] How to bind a register variable with a given general purpose register?

or you can just add a built-in function in c frontend "readadcreg()" and emit it as llvm.zhu.readadcreg(), so you can just call the built-in function to get the adc register value. On 2010-1-4 21:27, Demon(Xiangyang) Zhu 朱向阳 wrote: > Hi Ether, > > Thank you very much. I will try it soon as your description. > > Regards > > ________________________________________

hi zhu, i am not sure if your c frontend support "int ADC asm("GPR13");" i think you could: 1. add a attribute "GPR13"(or a more meaningful name like "adcreg") and the corresponding handler, so you code "int ADC asm("GPR13");" became "int ADC __attribute__((GPR13));" 2. add a intrinsic functions like

According to your description i should not use the system libstdc++ and i need to specify the OTHER compiler libstdc++. But i don't where the OTHER compiler libstdc++ is. Is the OTHER compiler libstdc++ contained in llvm-2.5.tar.gz? if not where can i get it? 2009/10/20, Duncan Sands <baldrick at free.fr>: > > Hi Heyu Zhu, > > Then then the error is: >>

Hi everyone, It seems variable arguments is not support by mips backend in llvm-2.6. int func(int i, ...) { return 0; } llvm-gcc func.c -emit-llvm -c -O3 -o func.bc llc func.bc -relocation-model=static -march=mips -O0 -o func.s Command llc fails: llc:SelectionDAGBuilder.cpp:6440:void llvm::SelectionDAGISel::LowerArguments( llvm::BasicBlock):Assertion 'Invals.size() ==

Hi, When i make LLVM with llvm-2.5.tar.gz an error occurs. The step is below tar -zxvf llvm-2.5.tar.gz cd llvm-2.5-tar.gz make ENABLE_OPTIMIZED=1 Then then the error is: /tools/IUS611/tools/lib/libgcc_s.so.1: version `GCC_4.2.0' not found (required by /usr/lib/libstdc++.so.6) What shall i do to avoid it? I am a newbie, maybe it's a foolish question Regards -------------- next

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

Hi, On Wed, Feb 3, 2010 at 3:57 AM, Heyu Zhu <zhu.heyu at gmail.com> wrote: > Hi everyone, > > It seems variable arguments is not support by mips backend in llvm-2.6. > > int func(int i, ...) { >   return 0; > } > > llvm-gcc    func.c -emit-llvm -c  -O3   -o func.bc > llc    func.bc -relocation-model=static  -march=mips -O0  -o func.s > > Command llc

Hi everyone The c code is like below extern int function_0(int, int); int main(){ return function_0(8, 9); } I compile it as below llvm-gcc main.c -emit-llvm -c -O3 -o main.bc llc main.bc -relocation-model=static -march=mips -O0 -o main.s It seems no argument is provided to function_0 ... addiu $sp, $sp, -8 sw $ra, 0($sp) jal function_0

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Hi, The gcc version in my system is 3.4.6 During make display error message and stop cc1plus:error: unrecognzied command line option -Wno-variadic-macros Must i update gcc to version 4.2.0 or above to resolve the problem? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello everyone, I want to generate machine code for target thumb, so run with bit code test.bc llc -march thumb test.bc -filetype obj -o test.o It doesn't generate test.o but show a message: "target doesn't support generation of this file type!" What's wrong? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi everyone, I try to add an instruction to x86. The instruction is a multiply-add instruction MULADD A, B, C; //A = A + B * C. I use the instruction by inline assemble as below int x, y, z; ..... .... x = 0; asm("MULADD %0, %1, %2":"=r"(x):"0"(x), "r"(y), "r"(z)); ..... .... The backend does allocate registers %edx, %edi, %esi for x,y, z

Hi Heyu Zhu, > Then then the error is: > > /tools/IUS611/tools/lib/libgcc_s.so.1: version `GCC_4.2.0' not found > (required by /usr/lib/libstdc++.so.6) you can get this if you compile C++ code using a different compiler to your system compiler. Based on the error message, your system compiler is gcc-4.2 and the other compiler is probably gcc-4.3 or later. What has happened

Hi Heyu Zhu, > According to your description i should not use the system libstdc++ and > i need to > specify the OTHER compiler libstdc++. But i don't where the OTHER compiler > libstdc++ is. > Is the OTHER compiler libstdc++ contained in llvm-2.5.tar.gz? if not > where can i get it? this has nothing to do with llvm, you would have the same problem with any C++ code that

On Oct 20, 2009, at 8:29 PM, Heyu Zhu wrote: > Hi, > > The gcc version in my system is 3.4.6 > During make display error message and stop > > cc1plus:error: unrecognzied command line option -Wno-variadic-macros > > Must i update gcc to version 4.2.0 or above to resolve the problem? That is a sign that your native GCC is not new enough, upgrading to 4.2 or later should

Hi Heyu Zhu, > I want to generate machine code for target thumb, so run > with bit code test.bc > > llc -march thumb test.bc -filetype obj -o test.o > > It doesn't generate test.o but show a message: > > "target doesn't support generation of this file type!" writing object code directly is not supported yet (though it is being worked on), so for

Hi Duncan, Is it to say llvm-2.5 has no assembler and linker for target thumb and llvm-2.5 can only generate assembler file for the time being? Thanks 2009/11/4, Duncan Sands <baldrick at free.fr>: > > Hi Heyu Zhu, > > I want to generate machine code for target thumb, so run >> with bit code test.bc >> llc -march thumb test.bc -filetype obj -o test.o >>

On Dec 29, 2009, at 3:09 AM, Heyu Zhu wrote: > Hi everyone, > > I try to add an instruction to x86. The instruction is a multiply-add instruction > MULADD A, B, C; //A = A + B * C. > I use the instruction by inline assemble as below > > int x, y, z; > ..... .... > x = 0; > asm("MULADD %0, %1, %2":"=r"(x):"0"(x), "r"(y),

Hello everyone, The target is designed by our company. It has general instructions and certain special instructions for audio/video application. It's my first time to learn comipler, so I really appreciate your help. What materials should i study step by step to build a llvm compiler backend? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello everyone, I try to write target description by reference to existing backends. Target description declares an instruction as below: def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo, "mov", " $dst, $src", [(set GPR:$dst, so_imm2part:$src)]>; I find 'set' declared in file