similar to: [LLVMdev] Question to use inline assemble in X86

On Dec 29, 2009, at 3:09 AM, Heyu Zhu wrote: > Hi everyone, > > I try to add an instruction to x86. The instruction is a multiply-add instruction > MULADD A, B, C; //A = A + B * C. > I use the instruction by inline assemble as below > > int x, y, z; > ..... .... > x = 0; > asm("MULADD %0, %1, %2":"=r"(x):"0"(x), "r"(y),

Hi All, I am working on writing pass in LLVM and interested in doing function permutation at intermediate representation byte code level? If I have lets say C program having three functions and its corresponding IR bytecode. void findLen(char a[10]) { int tmp = strlen(a); printf("Len is : %d\n", tmp); } void muladd(int a, int b, int c) { int tmp = a + b; int tmp1 = tmp *

Can anybody point me at any resources that would explain how to optimize mdct_backward for a cpu with a fused multiply-accumute unit? >From what I understand from responses to my older postings, Tremor's mdct_backward could be rewritten to take advantage of a muladd. My target machine can do either two-wide 32x32 + Accum(64) -> Accum(64) integer muladd or eight-wide 16x16 + Accum(32)

Hi everyone, There are 16 GPRs in my RISC, but in fact GPR13 is read-only and connected to output of an A/D converter. It would be very convenient if i could bind a register variable with GPR13. Because i am a newbie i don't know how my llvm backend can support that. I plan to implement it as below. A. first declare a global variable in c-code int ADC asm("GPR13"); B. If

Hello everyone, I want to generate machine code for target thumb, so run with bit code test.bc llc -march thumb test.bc -filetype obj -o test.o It doesn't generate test.o but show a message: "target doesn't support generation of this file type!" What's wrong? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Sanjay, You are right. I tried XL and gcc 4.8.2 for PPC and I also got multiply-and-add operations. I supported my statement on what I read in the gcc man page. -ffast-math is used in clang to set fp-contract to fast (default is standard) and in gcc it activates (among others) the flag -funsafe-math-optimizations whose description includes: "Allow optimizations for floating-point

Hi all, I am trying to disassemble *.bc to assemble code by using llvm-dis command, but what I got is like the following. So how could I get the assemble code like objdump? I mean the memory address for each instruction. Thanks Qiuyu llvm-dis: .text .align 16 .globl adpcm_coder .type adpcm_coder, @function adpcm_coder: .LBBadpcm_coder_0: # entry sub %ESP, 116 mov DWORD PTR [%ESP + 12],

According to your description i should not use the system libstdc++ and i need to specify the OTHER compiler libstdc++. But i don't where the OTHER compiler libstdc++ is. Is the OTHER compiler libstdc++ contained in llvm-2.5.tar.gz? if not where can i get it? 2009/10/20, Duncan Sands <baldrick at free.fr>: > > Hi Heyu Zhu, > > Then then the error is: >>

Hi everyone, It seems variable arguments is not support by mips backend in llvm-2.6. int func(int i, ...) { return 0; } llvm-gcc func.c -emit-llvm -c -O3 -o func.bc llc func.bc -relocation-model=static -march=mips -O0 -o func.s Command llc fails: llc:SelectionDAGBuilder.cpp:6440:void llvm::SelectionDAGISel::LowerArguments( llvm::BasicBlock):Assertion 'Invals.size() ==

Hi, When i make LLVM with llvm-2.5.tar.gz an error occurs. The step is below tar -zxvf llvm-2.5.tar.gz cd llvm-2.5-tar.gz make ENABLE_OPTIMIZED=1 Then then the error is: /tools/IUS611/tools/lib/libgcc_s.so.1: version `GCC_4.2.0' not found (required by /usr/lib/libstdc++.so.6) What shall i do to avoid it? I am a newbie, maybe it's a foolish question Regards -------------- next

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

Hi Heyu Zhu, > I want to generate machine code for target thumb, so run > with bit code test.bc > > llc -march thumb test.bc -filetype obj -o test.o > > It doesn't generate test.o but show a message: > > "target doesn't support generation of this file type!" writing object code directly is not supported yet (though it is being worked on), so for

Hi everyone The c code is like below extern int function_0(int, int); int main(){ return function_0(8, 9); } I compile it as below llvm-gcc main.c -emit-llvm -c -O3 -o main.bc llc main.bc -relocation-model=static -march=mips -O0 -o main.s It seems no argument is provided to function_0 ... addiu $sp, $sp, -8 sw $ra, 0($sp) jal function_0

Hi, On Wed, Feb 3, 2010 at 3:57 AM, Heyu Zhu <zhu.heyu at gmail.com> wrote: > Hi everyone, > > It seems variable arguments is not support by mips backend in llvm-2.6. > > int func(int i, ...) { >   return 0; > } > > llvm-gcc    func.c -emit-llvm -c  -O3   -o func.bc > llc    func.bc -relocation-model=static  -march=mips -O0  -o func.s > > Command llc

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Hi, The gcc version in my system is 3.4.6 During make display error message and stop cc1plus:error: unrecognzied command line option -Wno-variadic-macros Must i update gcc to version 4.2.0 or above to resolve the problem? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello, I am not sure whether this is a clang issue, an LLVM issue, or both; but clang chokes when parsing expanded macros from the glibc /usr/include/bits/fenvinline.h with an error like: ./boost/math/tools/config.hpp:279:10: error: invalid input constraint 'i#*X' in asm feclearexcept(FE_ALL_EXCEPT); ^ /usr/include/bits/fenvinline.h:56:11: note: expanded from macro

Hi Jean-Marc I'm trying to integrate your speex codec on our custom Blackfin board. The board is not uCLinux compatible and there is no chance that it will ever be. I am using ADI-supplied VisualDSP++ IDE and corresponding toolchain. As long as I am compiling "C"-only version of the library everything is fine. VisualDSP++ produces working library. There is only one not so minor

Am 13.06.2017 um 02:05 schrieb Ilia Mirkin: > On Mon, Jun 12, 2017 at 7:57 PM, Roland Scheidegger <sroland at vmware.com> wrote: >> FWIW surely on nv50 you could keep a single mad instruction for umad >> (sad maybe too?). (I'm actually wondering if the hw really can't do >> unfused float multiply+add as a single instruction but I know next to >> nothing

On Fri, 2012-04-27 at 14:54 -0500, Hal Finkel wrote: > There is a comment in the file which reads: > > /* The weird 'i#*X' constraints on the following suppress a gcc > warning when __excepts is not a constant. Otherwise, they mean the > same as just plain 'i'. */ [sinp] > ("mtfsb0 %s0" : : "i#*X"(__builtin_ffs (__excepts))); [snip]