similar to: [LLVMdev] problem when use inline asm for msp430 target

Hello > inline asm code is like below: > > void test(unsigned short a) { >    asm("myinstr          my16bitreg, %0"::"r"(a)); > } > I want it generate instruction "myinstr          my16bitreg, r15" > > I execute > llc test.bc -march = msp430 -o test.s > then it reports > "LLVM ERROR: Couldn't allocate input reg for constraint

Hi Anton, Need i write additial c/c++/td code for my target to support inline asm? Regrads 2009/12/18 Anton Korobeynikov <anton at korobeynikov.info> > Hello > > > inline asm code is like below: > > > > void test(unsigned short a) { > > asm("myinstr my16bitreg, %0"::"r"(a)); > > } > > I want it generate instruction

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

Hi Gents, For those of us with out-of-tree backends which are not 32bit, the msp430 backend is a useful vehicle for examining changes and testing out ideas. So I was wondering about enabling debug output on the MSP430 backend so that I can illustrate a few issues to Adrian and you on the variable pieces side. (there doesn't appear to be any specific person claiming the msp430 code right

On Thu, Jul 6, 2017 at 1:35 AM, Nicholas Wilson < iamthewilsonator at hotmail.com> wrote: > Luís, try using the -no-integrated-as flag to execute the assembler for > you. > We should probably make that the default for MSP430. > Cool. When I did that on macOS, LDC generated a lot of complaints, possibly because it is assuming mach-o files. I tried changing from -mtriple=msp430

On Thu, Jul 6, 2017 at 2:19 AM, Tim Northover <t.p.northover at gmail.com> wrote: > On 5 July 2017 at 17:51, Luís Marques via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Cool. When I did that on macOS, LDC generated a lot of complaints, > possibly > > because it is assuming mach-o files. I tried changing from > -mtriple=msp430 > > to

Hello, I have a user asking about msp430 support for Zig. When they try to target msp430, this error is triggered: if (target_machine->addPassesToEmitFile(MPM, dest, ft)) { *error_message = strdup("TargetMachine can't emit a file of this type"); return true; } I tried using clang alone: clang -c add.c -target msp430-unknown int add(int

Hello, While trying to find out why the LDC compiler refuses to generate object code for MSP430 targets (but generates MSP430 assembly or LLVM IR/bitcode), I came across the following apparent inconsistency. This works: $ clang --target=msp430 -c test.c This doesn't work: $ clang --target=msp430 -S -emit-llvm test.c $ llc -filetype=obj test.ll /opt/msp430/bin/llc: target does not support

Hello, Yesterday I noticed that MSP430 argument passing is broken in trunk; see http://llvm.org/PR6573 for details and testcases. The problem is that calls aren't being preceded by instructions that put the arguments into registers. I backtracked my working copy and then stepped forward until it broke between r98937 and r98938. Refining further, I found that rolling back the

On Fri, Jun 11, 2010 at 2:55 PM, Ben Ransford <ransford at cs.umass.edu> wrote: > Yesterday I noticed that MSP430 argument passing is broken in trunk; > see http://llvm.org/PR6573 for details and testcases.  The problem is > that calls aren't being preceded by instructions that put the > arguments into registers.  I backtracked my working copy and then > stepped forward

Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a reviewer.

Interested in building a speex codec (basically audio <-> speex <-> data stream) using TI's small MSP430 microcontroller. Is there any way to estimate feasibility based on CPU requirements? Example - speex is happily encoding on an old Pentium-1 processor (166 MHz) using about half the CPU (as reported under Linux); the TI microcontrollers are much slower yet (8-16-25 MHz) and

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued

Please CC me. I will review. On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a

Thank you. I don't know what CC means, but I will ping the diff so you can get an email. > On May 23, 2016, at 15:06, Anton Korobeynikov <anton at korobeynikov.info> wrote: > > Please CC me. I will review. > > On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Who is a code owner for MSP430 target? I

Hi all, I have problem with specifying complex patterns in PPC Isel backend. I would like to fetch few instructions into one like that: def MatchPAT1 : Pat<(or (or (shl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)), 0xFF0000) ), (or (srl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)),0xFF00) )), (myinstr GPRC:$rA)>; That pattern

Hi All, While implementing a custom 16 bit target for academical and demonstration purposes, I unexpectedly found that LLVM was not really ready for 8 bit and 16 bit targets. Let me expose why. Target backends can be divided into two major categories, with essentially nothing in between: Type 1: The big 32 or 64 bit targets. Heavily pipelined with expensive branches, running at clock

On Wed, Nov 13, 2019 at 12:26 PM Joan Lluch via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > In relation to the subject of this message I got my first round of patches successfully reviewed and committed. As a matter of reference, they are the following: > > https://reviews.llvm.org/D69116 > https://reviews.llvm.org/D69120 >

On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com> wrote: > I have an instruction that takes no operands, and produces two results, in two consecutive cycles. > > I tried both of the following to my Schedule.td file: > > InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, > InstrItinData<IIMyInstr, [InstrStage<1,

On 09/05/2013 18:25, Andrew Trick wrote: > > On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com > <mailto:fraser at codeplay.com>> wrote: > >> I have an instruction that takes no operands, and produces two >> results, in two consecutive cycles. >> >> I tried both of the following to my Schedule.td file: >> >>