similar to: [LLVMdev] Early-clobber constraint in TableGen

On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > For a usage example, I've included in the patch the modification to > use the constraint for the STREX ARM instruction. Your example is: constraints = "@early $success" Why not spell it as: constraints = "$success != $src", "$success != $ptr" The grammar would change to something like:

On Dec 15, 2009, at 5:08 PM, David Greene wrote: > On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > >> For a usage example, I've included in the patch the modification to >> use the constraint for the STREX ARM instruction. > > Your example is: > > constraints = "@early $success" > > Why not spell it as: > > constraints =

On Tuesday 15 December 2009 19:52, Jim Grosbach wrote: > Do you have specific examples in mind that would be expressible with > something more complicated that aren't handleable via an early-clobber > constraint? Not offhand, no. I'm mostly concerned about the readability of .td files. > Perhaps spelling it out more fully with "earlyclobber" rather than >

On Dec 15, 2009, at 6:26 PM, David Greene wrote: > On Tuesday 15 December 2009 19:52, Jim Grosbach wrote: > >> Do you have specific examples in mind that would be expressible with >> something more complicated that aren't handleable via an early- >> clobber >> constraint? > > Not offhand, no. I'm mostly concerned about the readability of .td >

On Wednesday 16 December 2009 12:54, Jim Grosbach wrote: > > That's better. Is there any way you could convince TableGen to > > recognize > > that 'constraints = "$success != $src", "$success != $ptr"' is > > semantically > > equivalent to earlyclobber? Maybe check that the common operand in > > both > > contraints is

On Fri, Sep 25, 2015 at 2:17 PM, JF Bastien <jfb at google.com> wrote: > Looks like this was caused by r248294. Author CC'ed. > > On Fri, Sep 25, 2015 at 1:46 PM, Richard Pennington via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> >> Hi, >> >> I was compiling libc++ with a recent TOT (248571) and when I got to the >> ARMv6, I got a

Use an early clobber on addr to avoid the extra rorl instruction at the end of _set_tssldt_desc. Also, get some C type checking on the descriptor struct here. Patch-base: 2.6.13-rc5-mm1 Patch-keys: i386 desc cleanup optimize Signed-off-by: Zachary Amsden <zach@vmware.com> Index: linux-2.6.13/include/asm-i386/desc.h =================================================================== ---

Use an early clobber on addr to avoid the extra rorl instruction at the end of _set_tssldt_desc. Also, get some C type checking on the descriptor struct here. Patch-base: 2.6.13-rc5-mm1 Patch-keys: i386 desc cleanup optimize Signed-off-by: Zachary Amsden <zach@vmware.com> Index: linux-2.6.13/include/asm-i386/desc.h =================================================================== ---

Use an early clobber on addr to avoid the extra rorl instruction at the end of _set_tssldt_desc. Also, get some C type checking on the descriptor struct here. Signed-off-by: Zachary Amsden <zach@vmware.com> Index: linux-2.6.13/include/asm-i386/desc.h =================================================================== --- linux-2.6.13.orig/include/asm-i386/desc.h 2005-08-08

Use an early clobber on addr to avoid the extra rorl instruction at the end of _set_tssldt_desc. Also, get some C type checking on the descriptor struct here. Signed-off-by: Zachary Amsden <zach@vmware.com> Index: linux-2.6.13/include/asm-i386/desc.h =================================================================== --- linux-2.6.13.orig/include/asm-i386/desc.h 2005-08-08

Hi Tim ---------------------------------------- > Date: Wed, 8 Apr 2015 06:53:44 -0700 > Subject: Re: [LLVMdev] __sync_add_and_fetch in objc block for global variable on ARM > From: t.p.northover at gmail.com > To: alexey.perevalov at hotmail.com > CC: llvmdev at cs.uiuc.edu > >> in disas I see dmb ish instruction, but I don't know is it enough. > > There should

> I''m not mad keen on propagating these sorts of asm atomic operations throughout > our code base. Other options would be: gcc has atomic builtins to do this kind of work. I don''t know about arm, but they do the job in x86 http://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html so atomic_inc(val) -> __sync_fetch_and_add(val, 1) and likewise for dec/sub Andres

flight 18753 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/18753/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-xl-win7-amd64 8 guest-saverestore fail REGR. vs. 18750 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-pcipt-intel 9 guest-start fail

Hi I want to enumerate all vectors of length "J", whose elements are integers in the range 1 to S, without regard to ordering. With J=S=3, the combinations are as follows: [,1] [,2] [,3] [1,] 1 1 1 [2,] 1 1 2 [3,] 1 1 3 [4,] 1 2 2 [5,] 1 2 3 [6,] 1 3 3 [7,] 2 2 2 [8,] 2 2 3 [9,] 2

Hello community, I faced with bug in multithread environment in objective C code which using dispatch_async and block, __sync_add_and_fetch increments global variable. But in case of many..many threads> 5, after every __sync_add_and_fetch got damaged ... int32_t count = 0; ... int main(int argc, char *argv[]) {    for (i = 1; i < 32; ++i) {      ...         char* name;        

Can someone explain what MCInst is vs. MachineIntr? I'm porting some patches we have here that affect MachineInstrs and am wondering whether I need to make similar changes in MCInst. Why do we have two machine instruction representations? -Dave

Dear all, I was wondering if it is possible in TableGen to either: 1. Selectively define an instruction depending on an SDNode's properties, e.g. if the SDNode is not commutative. 2. Override/ignore the TableGen error given when a commutative node has an immediate on the LHS. My case comes from trying to define a generic ALU operation multiclass for my target, which includes a

Hello everyone, Let me (re)present a question that might have previously been discussed, but did not result in any code (AFIK). How do we represent a _conditional_ assignment (def) in a bundle MI? More contents - currently we expose internal def/use/kill information to a bundle header - something like this: BUNDLE %PC<imp-def>, %R0<imp-def>, %P0<imp-use,kill>,

Ivan, Sorry, no, I wasn't clear enough. Both "op dst_reg,immediate,src_reg" and "op dst_reg,src_reg,immediate" are allowed in the ALU ops. For most instructions these are two different things - e.g. sub a,5,b is different from sub,a,b,5 obviously - but for things like add they just define the same thing. My problem is that LLVM won't allow immediates on the LHS of

On 4/28/2015 7:13 PM, Alex L wrote: > > > 2015-04-28 16:26 GMT-07:00 Matthias Braun <matze at braunis.de > <mailto:matze at braunis.de>>: > > For that use case it is worth keeping the following things in mind: > - Please try to keep the output of the various dump functions, esp. > MachineInstr::dump(), MachineOperand::dump(), >