similar to: [LLVMdev] Back-end with general purpose registers

I know, it's a strange question but I want install Wine on windows Why? Because of compatibility, I use XP and I want use win 3.x applications, and vista applications. I think wine it's a possibility, I use it on linux but I don't want reboot all time. Je sais, c'est un question bizarre mais je veux installer Wine sous windows Pourquoi? ? cause se la compatibilit?, j'utilise

I have a program that sets up a server on UDP port 59; it runs with no problem under windows XP. Under wine it fails, the log shows "Permission denied" for the WS_bind function. Has anyone else seen this? Does anyone know how to work around this? trace:winsock:WSAStartup succeeded trace:winsock:WS_socket af=2 type=1 protocol=0 trace:winsock:WSASocketA af=2 type=1 protocol=0

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let

I have a back end which has both scalar and vector registers that alias each other. I'm having a problem generating the ISel from tablegen that appears only when a vector register class is declared to contain integer vectors. At that moment tablegen doesn't seem to be able to infer integer types in patterns that it was able to before, but I'm not clear on why that's the

Hi all, I was wondering if it is possible to match the icmp and fcmp assembly language instructions in the code generator. For example, for the following code: %cmp = icmp sgt i32 %tmp, %tmp1 ; <i1> [#uses=1] br i1 %cmp, label %if.then, label %if.else We would like to see something like: SGT cmp, tmp, tmp1 BR cmp lbl However, I can't see any case in the back-ends

Hi all, I was wondering if it is possible to stop floating-point constants being converted to use the constant pool? As for our back-end we would like to be able to treat floating point constants the same way integer constants are treated instead of having to go via the constant pool. Thanks for your help, Rob - This message is subject to Imagination Technologies' e-mail terms:

Hi, I was wondering if it was possible to detect if a function is recursive in a back-end. For instance, I'd like to be able to say: "If this function we are about to call is recursive, store the return address to the stack, if it isn't we don't need a stack so do nothing". Does anyone know if this is possible? Thanks, Rob - This message is subject to Imagination

On Sun, 22 Apr 2007, Christopher Lamb wrote: > I have a back end which has both scalar and vector registers that > alias each other. I'm having a problem generating the ISel from > tablegen that appears only when a vector register class is declared > to contain integer vectors. At that moment tablegen doesn't seem to > be able to infer integer types in patterns that it was

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

On Thu, 04 Jun 2009 22:55:04 +0200, Pertti Kellomäki <pertti.kellomaki at tut.fi> wrote: > Hi Adam, > > John is right, the TCE stuff would be useful for you. Our > compiler targets a processor template that the designer can > populate pretty freely. The compiler then reads the architecture > description and creates an LLVM backend on the fly. > > Please don't

Digging deeper... 1. Is there a good reason that v2f32 types are excluded from the isFloatingPoint filter? Looks like a bug to me. v2f32 = 22, // 2 x f32 v4f32 = 23, // 4 x f32 <== start ?? v2f64 = 24, // 2 x f64 <== end static inline bool isFloatingPoint(ValueType VT) { return (VT >= f32 && VT <= f128) || (VT

Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include

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Hi all, We are looking to try and reduce the size of the clang and LLVM libraries and were wondering if anyone had any advice on how to do this. All we want is to be able to compile from a single language to a single back-end and for that back-end to emit instructions; we don't care about anything else. Currently we are building LLVM to use only our target, so that is OK. Is it possible to

On Apr 18, 2007, at 2:07 PM, Evan Cheng wrote: > > On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > >> I noticed that the TableGen code emitter generator assumes that >> the instruction fields are declared in the instruction format in >> the same order that operands are defined. This seems like a bad >> dependence to me, and that TableGen should match

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Hi folks, I'm trying to set up shared folders via symlinking and have come across a problem. I created a folder for one user, then symlinked it to another. I figured that one thing that is likely to happen at some point is that user 2 is going to decide they don't want to look at that folder any more, and will delete it, so I tried this. Much to my relief, it didn't delete the actual

On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > I noticed that the TableGen code emitter generator assumes that the > instruction fields are declared in the instruction format in the > same order that operands are defined. This seems like a bad > dependence to me, and that TableGen should match the name of field > declared in the instruction with the name of the

I noticed that the TableGen code emitter generator assumes that the instruction fields are declared in the instruction format in the same order that operands are defined. This seems like a bad dependence to me, and that TableGen should match the name of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See