similar to: [LLVMdev] Question about 'side-effect' and 'chain'

Hi, > 1 What side effects do operatios of loads/stores/calls/returns have? > (maybe i don't understand concept of side effect ) suppose you do a store to a memory location, and then load from the memory location. This is not the same as first doing the load and then only afterwards doing the store! How to represent the order in the SDAG? The SDAG is not a linear sequence of

Hello to all. I’m new to Xen and virtualization. We are a small business, with up to 10 users. In order to reduce our TCO, I’m thinking on installing virtual machines to cut down costs and maintenance. 1) A 10/100/1000 network to which 1 virtual machine server attached 2) The different virtual server to run in it are : a. MS Windows 2003/2008 Domain controller, DHCP and

Hi llvm-dev, I am currently writing a backend for an architecture I am designing in my bachelor's thesis and recently came across the GlobalISel Selection Framework. Should already start using this over the more common Selection DAG? Being new llvm backend development, I am not sure if GlobalISel would be "easier" to implement than ISelDAG and if there is any decent documentation on

You are right: select in SDAG has to be poison-blocking as well, otherwise the current lowering from IR's select to SDAG's select would be wrong. Which makes the select->or transformation incorrect at SDAG level as well. I guess until recently people believed that poison in SDAG wasn't much of a problem (myself included). I was convinced otherwise with the test cases that

Hi all, I'm working on a new pass to optimize comparison chains. Motivation Clang currently generates inefficient code when dealing with contiguous member-by-member structural equality. Consider: struct A { bool operator==(const A& o) const { return i == o.i && j == o.j; } uint32 i; uint32 j; }; This generates: mov eax, dword ptr [rdi] cmp eax,

> Transforms/InstCombine/select.ll > ================================ > define i1 @trueval_is_true(i1 %C, i1 %X) { >  %R = select i1 %C, i1 1, i1 %X >  ret i1 %R > } > => > define i1 @trueval_is_true(i1 %C, i1 %X) { >  %R = or i1 %C, %X >  ret i1 %R > } > ERROR: Target is more poisonous than source (when %C = #x1 & %X = poison) > > (there are

On 10 May 2014, at 18:14, Tim Northover <t.p.northover at gmail.com> wrote: >> The easiest solution would be to extend the cmpxchg instruction with a >> weak variant. It is then trivial to map load, modify, weak-cmpxchg to >> load-linked, modify, store-conditional (that is what weak cmpxchg was >> intended for in the C[++]11 memory model). > > That would

I am hoping that someone can offer advice on a somewhat unusual issue that I am facing with the SDAG. Namely, I am trying to implement some custom operations that do very specific things on multiple registers at a time. The operations themselves will simply be intrinsics since there are no equivalent operations in IR/SDAG. However, handling the types seems rather tricky. One approach I tried is

> On Jul 3, 2019, at 4:43 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > -----Original Message----- > From: David Greene <dag at cray.com> > Sent: Wednesday, July 3, 2019 2:44 PM > To: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > Cc: Krzysztof Parzyszek <kparzysz at quicinc.com> > Subject: [EXT] Re:

Hi, As part of the effort to bring up GlobalISel, I would like your feedbacks on the best way to map LLVM IR values into MachineInstr values (virtual registers), in particular when aggregate types get involved. I am looking for a long term solution. Short term is to replicate SDAG solution. ** Context ** The first step of GlobalISel is to translate the LLVM IR into MachineInstr

Hi Hal, Thanks for your quick reply. > On Jan 14, 2016, at 4:53 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ----- Original Message ----- >> From: "Quentin Colombet via llvm-dev" <llvm-dev at lists.llvm.org> >> To: "llvm-dev" <llvm-dev at lists.llvm.org> >> Sent: Thursday, January 14, 2016 6:41:57 PM >> Subject: [llvm-dev]

hi, i'm writing a target dependent analysis on machine instruction level in llvm 2.0. the analysis needs to know if an inline assembly block reads from memory. the programmer is responsible to add 'm' constraints accordingly. i've seen the operand flags of the inline assembly SDNode and the machine instructions. but it seems that there is no difference between input and output

On Mon, Oct 10, 2016 at 8:31 PM, Chris Lattner <clattner at apple.com> wrote: > > On Oct 10, 2016, at 8:12 PM, Peter Collingbourne via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I wanted to summarise some discussion on llvm-commits [0,1] as an RFC, as > I felt it demanded wider circulation. > > Our support for references to absolute

Regarding the patches, there are two concerns AFAICT: 1. It’s a new instruction and as usual when introducing a new instruction it will require work for some time until most optimizations know about it, and to get rid of any potential perf regression. No big deal; we just need to do the work (and we have already done some of it). 2. The patch was written by a student, which may not have time to

> On Mar 18, 2016, at 1:47 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > Yes this IR does not build or shuffle any vector. Try to write a function that takes 8 ints and a pointer to a <4xi32>, builds two vectors with the 8 ints, > > This might sound like a dumb question, but how does one build a vector of ints out of regular ints in IR? See:

On 10 May 2014, at 16:18, Tim Northover <t.p.northover at gmail.com> wrote: > Actually, I really agree there. I considered it recently, but decided > to leave it as an intrinsic for now (the new IR expansion pass happens > after most optimisations so there wouldn't be much benefit, but if we > did it earlier and the mid-end understood what an ldrex/strex meant, I > could

On Sat, Mar 02, 2019 at 07:34:50PM -0800, Tim Northover wrote: > The biggest difference and problem I see would be building the thing, > since the target's headers are going to be needed, but they're > private. That means they're not shipped with LLVM so you'd need the > source (and an active build directory for the TableGenerated files, >

Hello all, The rich history of binary distribution formats based on LLVM [0][1][2][3][4] has proven LLVM's viability as a launchpad for stable platforms. However, issues with compilation time and compiler size have suggested that the translator must do too much, i.e. LLVM IR isn't a low-level enough virtual machine. So we introduce DAGIR ("dagger"), a new portable close to the

Hi all, For GlobalISel, we’re exploring options for implementing inlining optimizations for memcpy and friends. However, looking around the existing implementation, I don’t see anything that would particularly be problematic for us to do it at the IR level. The existing TLI hooks to specify how certain memcpy calls should be lowered doesn’t have anything too SelectionDAG specific, and an IR

I am wondering if there is a good/easy way to recover the original type of a pointer parameter in the SDAG. Here's the problem that I am dealing with: define <4 x i32> @test(i32* nocapture readonly %a) local_unnamed_addr #0 { entry: %0 = bitcast i32* %a to <4 x i32>* %1 = load <4 x i32>, <4 x i32>* %0, align 16, !tbaa !2 ret <4 x i32> %1 } The problem is