similar to: [LLVMdev] Duplicate Label in Generates ISel

On Thursday 03 December 2009 13:39, David Greene wrote: > I've got the following problem in the X86 selector generated by > TableGen: > > llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value > llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here > > This seems to happen because of a pattern I added for VEXTRACTF128 which > uses

On Thursday 03 December 2009 13:43, David Greene wrote: > Whoops, I forgot to fill in types: > > (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2) > > [(set DSTREGCLASS:$dst, > (v4f32 (extract_subreg > (vector_shuffle > (v8f32 undef), > (v8f32 SRCREGCLASS:$src1), >

Chris Lattner wrote: > However, I don't see any reason to base this off of strings. Instead > of passing down "f32" as a string, why not do something like this > pseudo code: > > class X86ValueType { > RegisterClass RegClass; > ... > } > > def X86_f32 : X86ValueType { > let RegClass = FR32; > ... }; > def X86_i32 :

On Jun 11, 2009, at 2:01 PM, David Greene wrote: > On Thursday 11 June 2009 12:28, Chris Lattner wrote: >>> >>> Yes. I want TableGen to be able to infer lots of stuff >>> programmatically. >>> This helps tremendously when specifying things like, oh, AVX. :) >> >> I don't see how this relates to regex's, and really don't want to

On Thursday 11 June 2009 12:28, Chris Lattner wrote: > On Jun 9, 2009, at 12:39 PM, David Greene wrote: > > On Tuesday 09 June 2009 14:34, Dan Gohman wrote: > >> Can you describe what problem you're trying to solve here? Does it > >> really need Regular Expressions? > > > > Yes. I want TableGen to be able to infer lots of stuff > >

On Jun 15, 2009, at 11:33 AM, David Greene wrote: > To reduce redundancy, developers must be able to write generic > patterns > like this: > > [(set DSTREGCLASS:$dst, // rr, rrr > (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))), > (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))], > > The substitution then fills in the appropriate types,

On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: > For example, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, >

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

Jakob Stoklund Olesen <jolesen at apple.com> writes: > The TableGen language seems to be growing Lisp macros from two > different directions. > > Che-Liang Chiou added a preprocessor with for loops, and David Greene > added multidefs. > > It seems that some kind of macro facility is needed, perhaps we should > discuss what it is supposed to look like? Don't

Jakob Stoklund Olesen <jolesen at apple.com> writes: > On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: > >> For example, I want to be able to do this: >> >> defm MOVH : >> vs1x_fps_binary_vv_node_rmonly< >> 0x16, "movh", undef, 0, >> // rr >> [(undef)], >> // rm >> [(set

Ok, so I've been chugging away at AVX and added some new features in TableGen to facilitate writing generic patterns. Here's an example: //===----------------------------------------------------------------------===// // Dummy defs for writing generic patterns //===----------------------------------------------------------------------===// def SRCREGCLASS; def DSTREGCLASS; def MEMCLASS;

On Oct 6, 2011, at 12:42 PM, David A. Greene wrote: > Jakob Stoklund Olesen <jolesen at apple.com> writes: > >> On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: >> >>> For example, I want to be able to do this: >>> >>> defm MOVH : >>> vs1x_fps_binary_vv_node_rmonly< >>> 0x16, "movh", undef, 0, >>>

On 22 February 2015 at 22:54, Hal Finkel <hfinkel at anl.gov> wrote: >> I tried setting the module's DataLayout to the engine's DataLayout. >> Don't see any improvement. >> The memcpy() is to perform a struct assign, so I tried replacing that >> with member by member store. >> But even then the loads are not being eliminated so I guess the >>

On Tuesday 16 June 2009 19:35, David Greene wrote: > So which is more intuitive and less error-prone? > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, > i32i8imm, "blend", "blend", "f32", 4>; > > or > > defm BLENDPS : sse41_avx_fp_binary_vector_osta_vintrinsic_rmi_rrmi<0x0C, >

On Monday 15 June 2009 14:35, Chris Lattner wrote: > > I suppose you could argue that additional parameters specifying > > the source and dest types could be passed, but why bother when > > it is already encoded in the mnemonic? That would just be > > adding error-prone redundancy. > > Why not synthesize the opcode string from the information passed down?

On Wednesday 10 July 2013 22:18:23 Jevin Sweval wrote: > http://www.cs.fsu.edu/~baker/devices/lxr/http/source/linux/arch/x86/include/ > asm/bitops.h#L68 > > Here is one example that I found. Are the inline assembly arguments > ambiguous in size? It would help us for sure to build the kernel and others. -- JS

On 23 February 2015 at 11:22, David Jones <djones at xtreme-eda.com> wrote: > You have not installed the DataLayout in the Module, as I had pointed out > earlier. > Hi David, I reported earlier that I tried this but there was no improvement. Well I ran another test to be sure. The results are below. As you can see the loads are still present. ; ModuleID =

Hello, I experienced a strange behaviour of callNextMethod when used in either initialize or any other S4 function method definition. Help says callNextMethod calls the next inherited method for the current function from where it is called with the same actual (non missing) arguments. This is OK. The problem appears when some formal arguments (in particular, S4 objects) of this function are

On 22 February 2015 at 20:58, David Jones <djones at xtreme-eda.com> wrote: > Not sure if this is your problem, but it was mine: > > You must create (or obtain) a DataLayout *and install it into the Module*. > > It is possible to generate machine code for IR and not install the > DataLayout into the Module. Rather, the DataLayout is used locally at the > point where code

The AVX saga continues. I am attempting to write a pattern for VEXTRACTF128 but am having some problems. My attempt looks something like this: defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg, MRMDestMem, "extractf128", undef, X86f32, X86i32i8, // rr [(set VR128:$dst,