Displaying 20 results from an estimated 1100 matches similar to: "[LLVMdev] Pat<> & tlbgen"
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
I have a few questions about the new vector shuffle matching code in the
x86 .td files. It's a big improvement over the old system and provides
the context that code generation for AVX needs. This is great!
I'm asking because I'm having some trouble converting some AVX patterns
over to the new system. I'm getting this error from tblgen:
VyPERM2F128PDirrmi: (set:isVoid
2009 Dec 02
5
[LLVMdev] Selecting Vector Shuffle of Different Types
The AVX saga continues.
I am attempting to write a pattern for VEXTRACTF128 but am having some
problems. My attempt looks something like this:
defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg,
MRMDestMem, "extractf128", undef, X86f32, X86i32i8,
// rr
[(set VR128:$dst,
2009 Dec 03
0
[LLVMdev] Duplicate Label in Generates ISel
On Thursday 03 December 2009 13:39, David Greene wrote:
> I've got the following problem in the X86 selector generated by
> TableGen:
>
> llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value
> llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here
>
> This seems to happen because of a pattern I added for VEXTRACTF128 which
> uses
2009 May 01
0
[LLVMdev] RFC: AVX Pattern Specification [LONG]
On May 1, 2009, at 2:47 PM, David Greene wrote:
> On Friday 01 May 2009 13:46, Chris Lattner wrote:
>> Right, a lot of these problems can be solved by some nice refactoring
>> stuff. I'm also hoping that some of the complexity in defining
>> shuffle matching code can be helped by making the definition of the
>> shuffle patterns more declarative within the td file.
2011 Feb 26
0
[LLVMdev] X86 LowerVECTOR_SHUFFLE Question
David Greene <dag at cray.com> writes:
> In ToT, LowerVECTOR_SHUFFLE for x86 has this code:
>
> if (X86::isUNPCKLMask(SVOp))
> getTargetShuffleNode(getUNPCKLOpcode(VT) dl, VT, V1, V2, DAG);
>
> why would this not be:
>
> if (X86::isUNPCKLMask(SVOp))
> return SVOp;
Ok, I discovered that Bruno did this in revisions 112934, 112942 and
113020 but the logs
2009 Dec 03
1
[LLVMdev] Duplicate Label in Generates ISel
On Thursday 03 December 2009 13:43, David Greene wrote:
> Whoops, I forgot to fill in types:
>
> (outs VR128:$dst), (ins VR129:$src1, i32i8imm:$src2)
>
> [(set DSTREGCLASS:$dst,
> (v4f32 (extract_subreg
> (vector_shuffle
> (v8f32 undef),
> (v8f32 SRCREGCLASS:$src1),
>
2009 Jun 04
2
[LLVMdev] TableGen Type Inference
Can someone explain why TableGen can't figure this out?
VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32
(bitconvert:isInt (ld:v4i32 addr:iPTR:$src)<<P:Predicate_memop>>)))
llvm/tblgen: In VCVTDQ2PS128rm: Could not infer all types in pattern!
The pattern as written looks like this:
[(set VR128:$dst, (v4f32 (sint_to_fp (bc_memopv4i32 addr:$src))))]
I'm
2009 Apr 30
6
[LLVMdev] RFC: AVX Pattern Specification [LONG]
Here's the big RFC.
A I've gone through and designed patterns for AVX, I quickly realized that the
existing SSE pattern specification, while functional, is less than ideal in
terms of maintenance. In particular, a number of nearly-identical patterns
are specified all over for nearly-identical instructions. For example:
let Constraints = "$src1 = $dst" in {
multiclass
2011 Sep 22
3
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
Hi Bruno,
> Some comments:
>
> + // Try to synthesize horizontal adds from adds of shuffles.
> + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
> + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&&
> + isHorizontalBinOp(LHS, RHS, true))
>
> 1) You probably want to do something like:
>
2009 Dec 03
2
[LLVMdev] Duplicate Label in Generates ISel
I've got the following problem in the X86 selector generated by
TableGen:
llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value
llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here
This seems to happen because of a pattern I added for VEXTRACTF128 which uses
extract_subreg:
[(set DSTREGCLASS:$dst,
(DSTTYPE (extract_subreg
2011 Sep 21
0
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
Hi Duncan,
On Wed, Sep 21, 2011 at 1:24 PM, Duncan Sands <baldrick at free.fr> wrote:
> This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from
> floating
> point additions and subtractions of appropriate vector shuffles. To do this
> I
> introduced new x86 FHADD and FHSUB opcodes. These need to be wired up
> somehow
> in the .td file to the appropriate
2011 Sep 22
0
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
The output of the avx-hadd program is
3 11 7 15
Preston
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands
Sent: Thursday, September 22, 2011 3:14 PM
To: Bruno Cardoso Lopes
Cc: LLVMdev
Subject: Re: [LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
Hi Bruno,
> Some comments:
2009 Dec 03
0
[LLVMdev] Selecting Vector Shuffle of Different Types
On Wed, Dec 2, 2009 at 3:46 PM, David Greene <dag at cray.com> wrote:
> The AVX saga continues.
>
> I am attempting to write a pattern for VEXTRACTF128 but am having some
> problems. My attempt looks something like this:
>
> defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg,
> MRMDestMem, "extractf128", undef,
2009 Mar 24
2
[LLVMdev] Reducing .td redundancy
Is it legal to do something like a !strconcat on a non-string entity? That
is, is there some operation that will let me do this (replace SOME_CONCAT with
an appropriate operator):
(WARNING! Hacked-up tablegen ahead!)
multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr,
SDNode OpNode> {
// Vector operation emulating scalar (fp)
2007 Aug 01
0
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
On Tue, 31 Jul 2007, [ISO-8859-1] Mikael Lepist� wrote:
> I was talking with aKor in #llvm how we could implement custom operation
> support for our ASIP architecture. We came into solution that the best
> way would be to write new custom operation intrinsic and optimization
> pass for raising certain type of function calls to those intrinsics
> (similar to raising mallocs).
>
2007 Aug 01
2
[LLVMdev] Adding custom operation intrinsic for ASIP architectures.
Chris Lattner wrote:
> On Tue, 31 Jul 2007, [ISO-8859-1] Mikael Lepist� wrote:
>> I was talking with aKor in #llvm how we could implement custom operation
>> support for our ASIP architecture. We came into solution that the best
>> way would be to write new custom operation intrinsic and optimization
>> pass for raising certain type of function calls to those intrinsics
2011 Feb 25
2
[LLVMdev] X86 LowerVECTOR_SHUFFLE Question
In ToT, LowerVECTOR_SHUFFLE for x86 has this code:
if (X86::isUNPCKLMask(SVOp))
getTargetShuffleNode(getUNPCKLOpcode(VT) dl, VT, V1, V2, DAG);
why would this not be:
if (X86::isUNPCKLMask(SVOp))
return SVOp;
I'm trying to add support for VUNPCKL and am getting into trouble
because the existing code ends up creating:
VUNPCKLPS
load
load
which is badness come selection
2012 Jul 26
2
[LLVMdev] X86 sub_ss and sub_sd sub-register indexes
All,
I've been trying to simplify the way LLVM models sub-register relationships a bit, and the X86 sub_ss and sub_sd sub-register indices are getting in the way. I want to get rid of them.
These sub-registers are special, they are only mentioned here:
let CompositeIndices = [(sub_ss), (sub_sd)] in {
def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
def
2009 May 01
4
[LLVMdev] RFC: AVX Pattern Specification [LONG]
On Friday 01 May 2009 13:46, Chris Lattner wrote:
> Right, a lot of these problems can be solved by some nice refactoring
> stuff. I'm also hoping that some of the complexity in defining
> shuffle matching code can be helped by making the definition of the
> shuffle patterns more declarative within the td file. It would be
> really nice to say that "this shuffle does a
2012 Jul 26
0
[LLVMdev] X86 sub_ss and sub_sd sub-register indexes
Jakob Stoklund Olesen <jolesen at apple.com> writes:
> These sub-registers are special, they are only mentioned here:
>
> let CompositeIndices = [(sub_ss), (sub_sd)] in {
> def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
> def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
> ...
I'm confused. Below you