Displaying 20 results from an estimated 5000 matches similar to: "[LLVMdev] How to build a llvm compiler backend for a specific target"
2009 Dec 18
2
[LLVMdev] Questions of instruction target description of MSP430
Hi everyone,
I am puzzled by several instruction defines in MSP430.
1
def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
"mov.w\t{$src, $dst}",
[ ]>;
Because it's an empty dag pattern[ ], by what does instuction selector
select intruction 'MOV16rr'?
2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =
2009 Dec 19
0
[LLVMdev] Questions of instruction target description of MSP430
Hi,
1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr.
2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued
2011 May 09
2
[LLVMdev] llvm backend
Hi,
I am writing you because I found in the LLVM site you have worked with
backends. I am writing a new backend for a processor I am working on,
because the compiler that comes with the processor design suite is really
messy (it is CoSy). I want to have a power compiler like llvm.
I read the "writing an LLVM compiler backend" and I have define almost all
the files, but I have problems
2009 Nov 04
2
[LLVMdev] newbie qustion: how to generate machine code for target thumb?
Hello everyone,
I want to generate machine code for target thumb, so run
with bit code test.bc
llc -march thumb test.bc -filetype obj -o test.o
It doesn't generate test.o but show a message:
"target doesn't support generation of this file type!"
What's wrong?
Thanks
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2009 Oct 20
3
[LLVMdev] Problem when build LLVM
According to your description i should not use the system libstdc++ and i
need to
specify the OTHER compiler libstdc++. But i don't where the OTHER compiler
libstdc++ is.
Is the OTHER compiler libstdc++ contained in llvm-2.5.tar.gz? if not where
can i get it?
2009/10/20, Duncan Sands <baldrick at free.fr>:
>
> Hi Heyu Zhu,
>
> Then then the error is:
>>
2010 Feb 03
2
[LLVMdev] Does mips backend support variable arguments in release version(llvm-2.6)?
Hi everyone,
It seems variable arguments is not support by mips backend in llvm-2.6.
int func(int i, ...) {
return 0;
}
llvm-gcc func.c -emit-llvm -c -O3 -o func.bc
llc func.bc -relocation-model=static -march=mips -O0 -o func.s
Command llc fails:
llc:SelectionDAGBuilder.cpp:6440:void
llvm::SelectionDAGISel::LowerArguments(
llvm::BasicBlock):Assertion 'Invals.size() ==
2009 Oct 20
3
[LLVMdev] Problem when build LLVM
Hi,
When i make LLVM with llvm-2.5.tar.gz an error occurs. The step is below
tar -zxvf llvm-2.5.tar.gz
cd llvm-2.5-tar.gz
make ENABLE_OPTIMIZED=1
Then then the error is:
/tools/IUS611/tools/lib/libgcc_s.so.1: version `GCC_4.2.0' not found
(required by /usr/lib/libstdc++.so.6)
What shall i do to avoid it?
I am a newbie, maybe it's a foolish question
Regards
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2010 Jan 28
1
[LLVMdev] question when -march=mips
Hi everyone
The c code is like below
extern int function_0(int, int);
int main(){
return function_0(8, 9);
}
I compile it as below
llvm-gcc main.c -emit-llvm -c -O3 -o main.bc
llc main.bc -relocation-model=static -march=mips -O0 -o main.s
It seems no argument is provided to function_0
...
addiu $sp, $sp, -8
sw $ra, 0($sp)
jal function_0
2016 Jan 21
1
NUT support for APC BackUPS Pro 900VA
Hi all,
I'm trying to configure Nut to connect to an APC BackUPS Pro 900VA.
This ups uses a serial port on which _simple_ or _smart_ signaling
should be spoken. I've connected the UPS to a serial port using the
original 940_0128A cable from APC.
Unfortunately I've not yet managed to read any data from the ups.
If I try to load the apcsmart driver it tells me that it cannot
communicate
2009 Jul 26
4
Wine Failing Miserably
I have a fully functional wine install on my Ubuntu parition. However, I have two relitively recent partitions, my Arch and my Xubuntu installs. I have attempted to get wine to work with either of thse installations and I have had absolutely no luck.
I have uninstalled wine competely. I have deleted my ~/.wine directory. I have compiled from source on both 32bit and 64bit systems. I have
2010 Feb 03
0
[LLVMdev] Does mips backend support variable arguments in release version(llvm-2.6)?
Hi,
On Wed, Feb 3, 2010 at 3:57 AM, Heyu Zhu <zhu.heyu at gmail.com> wrote:
> Hi everyone,
>
> It seems variable arguments is not support by mips backend in llvm-2.6.
>
> int func(int i, ...) {
> return 0;
> }
>
> llvm-gcc func.c -emit-llvm -c -O3 -o func.bc
> llc func.bc -relocation-model=static -march=mips -O0 -o func.s
>
> Command llc
2009 Nov 04
0
[LLVMdev] newbie qustion: how to generate machine code for target thumb?
Hi Heyu Zhu,
> I want to generate machine code for target thumb, so run
> with bit code test.bc
>
> llc -march thumb test.bc -filetype obj -o test.o
>
> It doesn't generate test.o but show a message:
>
> "target doesn't support generation of this file type!"
writing object code directly is not supported yet (though it is being worked
on), so for
2009 Nov 05
1
[LLVMdev] newbie qustion: how to generate machine code for target thumb?
Hi Duncan,
Is it to say llvm-2.5 has no assembler and linker for target thumb and
llvm-2.5 can only generate assembler file for the time being?
Thanks
2009/11/4, Duncan Sands <baldrick at free.fr>:
>
> Hi Heyu Zhu,
>
> I want to generate machine code for target thumb, so run
>> with bit code test.bc
>> llc -march thumb test.bc -filetype obj -o test.o
>>
2019 Jul 09
2
New User Questions - With Belkin USB
Hello all and thanks. I read here
<https://mn3m.info/posts/configure-ups-monitor-using-nut-on-debian/>
while searching around for my issue's resolution. In this I see that
this nut driver is creating and using an entry in /dev (in this case
ttyS0). So I "ll tty*" and see nothing with nut. Since this is a USB
UPS, I suppose I should be looking for something in /dev/ttyUSB*.
2010 Jan 04
5
[LLVMdev] How to bind a register variable with a given general purpose register?
Hi everyone,
There are 16 GPRs in my RISC, but in fact GPR13 is read-only and connected
to output of an A/D converter.
It would be very convenient if i could bind a register variable with GPR13.
Because i am a newbie i don't know how my llvm backend can support that.
I plan to implement it as below.
A. first declare a global variable in c-code
int ADC asm("GPR13");
B. If
2014 Sep 10
4
[LLVMdev] Leaks in PBQPBuilderWithCoalescing::build ?
Hi Lang,
In PBQPBuilderWithCoalescing::build, around line 360, we have code looking like:
…
PBQP::Vector newCosts(g.getNodeCosts(node));
addPhysRegCoalesce(newCosts, pregOpt, cBenefit);
g.setNodeCosts(node, newCosts);
…
I suspect the leak occurs around the setNodeCosts method, and I have trouble understanding how it handles the case where the node already has costs.
It seems to
2014 Sep 10
4
[LLVMdev] Leaks in PBQPBuilderWithCoalescing::build ?
Oooh. Neat. Thanks Dave. Please go ahead and commit that.
Arnaud - I have no idea whether Dave's patch will help with this bug, but
it's certainly worth testing.
- Lang.
On Wed, Sep 10, 2014 at 4:10 PM, David Blaikie <dblaikie at gmail.com> wrote:
> While I'm not sure where the leak is, using some pre-canned memory
> management might help...
>
> Attached is a
2015 Nov 20
2
[AArch64] bug in shrink-wrapping
Hi Arnaud,
Thanks for following up with that and sorry for the breakage.
Couple of comments:
MachineLoopInfo *MLI;
+ RegScavenger *RS;
Would it make sense to use a unique_ptr here?
That should eliminate the need of having explicit deletes.
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s
Add -enable-shrink-wrap=true and a second RUN line with -enable-shrink-wrap=false.
Then add check lines
2011 Mar 13
7
[LLVMdev] IndVarSimplify too aggressive ?
Hi all,
The IndVarSimplify pass seems to be too aggressive when it enlarge the induction variable type ; this can pessimize the generated code when the new induction variable size is not natively supported by the target. This is probably not an issue for x86_64, which supports natively all types, but it is a real one for several embedded targets, with very few native types.
I attached a patch to
2012 Apr 05
2
[LLVMdev] PBQP & CalcSpillWeights
Hi Lang,
Thanks a lot for taking time to look into this. I will test the fix soon and
let you know the results.
Cheers,
--
Arnaud de Grandmaison
On Tuesday, April 03, 2012 17:30:33 Lang Hames wrote:
> Hi Arnaud,
>
> Apologies for the delayed reply.
>
> Thank you for the excellent test case - it exposed a subtle bug in the
> colorability heuristic. This has been fixed in