Displaying 20 results from an estimated 40000 matches similar to: "[LLVMdev] Backend Function Pass"
2010 Jan 30
3
[LLVMdev] [patch] MicroBlaze Backend
> Your patch looks very clean. Some comments:
Heh, Jakob was faster :)
> - I think you have some literal tabs in your instruction descriptions.
The tabs can be seen in some other places as well. Also, there is a
"mix" of coding conventions in the files. It will be really nice to
use only one :)
> - Your tests are nice, but you could use some more of them. I would recommend
2009 Jun 04
1
[LLVMdev] Subsuming a memory node of a TargetGlobalAddress with a TargetConstant node
I am trying to removing a load to a TargetGlobalAddress in ISelDagToDag
that my backend does not support. The TargetGlobalAddress is assumed to
always be of ConstantInt or ConstantFP type, so this transformation is
valid. I am correctly able to modify the dag and remove all of the uses
of the node as specified in the attached before and after dot images.
The nodes in question is the
2011 Mar 18
3
[LLVMdev] [PATCH] OpenCL half support
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Villmow, Micah wrote:
<blockquote
2010 Jan 29
3
[LLVMdev] [patch] MicroBlaze Backend
I have been working on a LLVM backend for the MicroBlaze soft-processor:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze
Attached is the initial MicroBlaze patch. It does the following:
1. Adds mblaze as a target in configure and configure.ac
2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and include/llvm/Intrinsics.td
3. Adds mblaze
2011 Apr 01
2
[LLVMdev] Assert in VerifySDNode
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Duncan Sands
> Sent: Thursday, March 31, 2011 7:43 PM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Assert in VerifySDNode
>
> Hi Micah,
>
> > assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");
>
> you
2010 Jan 30
0
[LLVMdev] [patch] MicroBlaze Backend
On Jan 29, 2010, at 9:42 AM, Wesley Peck wrote:
> I have been working on a LLVM backend for the MicroBlaze soft-processor:
> http://www.xilinx.com/tools/microblaze.htm
> http://en.wikipedia.org/wiki/MicroBlaze
Very Cool!
> Attached is the initial MicroBlaze patch. It does the following:
> 1. Adds mblaze as a target in configure and configure.ac
> 2. Adds mblaze specific
2008 Dec 04
4
[LLVMdev] 32bit math being promoted to 64 bit
What optimization pass promotes 32 bit math operations to 64 bit
operations so I can disable it? I have code that works fine with
optimizations turned off but fails with it turned on because of this
stage.
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
2008 Dec 04
0
[LLVMdev] 32bit math being promoted to 64 bit
On Dec 4, 2008, at 8:58 AM, Villmow, Micah wrote:
> What optimization pass promotes 32 bit math operations to 64 bit
> operations so I can disable it? I have code that works fine with
> optimizations turned off but fails with it turned on because of this
> stage.
>
Do you have a testcase? An .ll file with no 64-bit operations, and
one optimization pass that introduces
2010 Jan 30
0
[LLVMdev] [patch] MicroBlaze Backend
On Jan 30, 2010, at 6:49 AM, Anton Korobeynikov wrote:
>> Your patch looks very clean. Some comments:
> Heh, Jakob was faster :)
I have taken care of everything Jakob mentioned except the extra test cases. I will get to these as soon as I can.
>
>> - I think you have some literal tabs in your instruction descriptions.
> The tabs can be seen in some other places as well.
2011 Apr 01
0
[LLVMdev] Assert in VerifySDNode
Hi Micah,
>>> assert(!isa<MemSDNode>(N)&& "Bad MemSDNode!");
>>
>> you can't use getNode to allocate a MemSDNode because it does not
>> allocate
>> enough memory (MemSDNode has extra fields beyond the operands).
>>
> [Villmow, Micah] Duncan, thanks for the reply. But I don't see how I am generating a MemSDNode with this
2009 Jan 30
1
[LLVMdev] Hitting assertion, unsure why
Well, I thought I knew how to fix the problem, but it seems my changes
didn't help at all. The frame index is being created when
FuncInfo->set() is called in SelectionDAGISel::runOnFunction().
This occurs at line 293 in SelectionDAGBuild.cpp when dealing with the
alloca instructions.
I've found the CopyToReg that is being issued occurs in LowerCALL and it
is this one that fails. When I
2012 Mar 06
0
[LLVMdev] OpenCL backend for LLVM
The person that wrote our structurizer agrees with your analysis. Too bad the licenses are incompatible, it would be nice to merge similar efforts.
> -----Original Message-----
> From: Simon Moll [mailto:simon.m.moll at googlemail.com]
> Sent: Tuesday, March 06, 2012 2:49 AM
> To: Villmow, Micah
> Cc: llvmdev at cs.uiuc.edu
> Subject: RE: [LLVMdev] OpenCL backend for LLVM
>
2011 Mar 18
0
[LLVMdev] [PATCH] OpenCL half support
> Maybe worth pointing out that there are architectures that natively support
> 16bit floating point in llvm. PTX, the new backend of which has just been
> added to 2.9 can handle fp16 -> fp32 conversion in hardware.
FWIW: there are already intrinsics for such conversions (currently
only used in ARM backend).
There is no need for new type if you want just to convert stuff.
--
With
2010 Dec 15
2
[LLVMdev] Optimization passes break machine instructions on new backend
But in the first version it's used on the next row:
%reg16388<def> = CMPrr %reg16384, %reg16385, %CFR<imp-def,dead>;
IntRegs:%reg16388,16384,16385
SKIPCOND 1, *%CFR<imp-use>*
Or doesn't that count?
Following are patters for cmp and skipcond:
def cmpcc : SDNode<"CSISD::CMP", SDTIntBinOp, [SDNPOutFlag]>;
let Defs = [CFR] in {
def CMPrr :
2020 Apr 17
1
Compare ISel
Good day LLVM-Dev,
I hope all are in good health.
We are currently implementing the compare operation for i64 type in our target.
The main difference of the i64 type compare to lower integer types is that it performs a library call instead of generating a compare instruction.
All is good until before ISelDAGToDAG class. We have observed that the difference in a compare operation for i32 and
2015 Mar 14
2
[LLVMdev] Add a backend
Yes, llvm::InitializeAllTargetMCs(void) does seem to be autogenerated. It
is _LLVMInitializeFooTargetMC that I can't find documented anywhere.
On Sat, Mar 14, 2015 at 12:05 AM, Anton Korobeynikov <
anton at korobeynikov.info> wrote:
> This function is autogenerated. You need also to change top-level
> configure / cmake files.
>
> On Sat, Mar 14, 2015 at 8:38 AM, Daniel
2012 Mar 06
2
[LLVMdev] OpenCL backend for LLVM
Hi Micah,
i just had a quick look at your structurizer. Here is what if found
(correct me, if i am mistaken):
* Our approaches for handling Loops with multiple exits are identical.
("Loop-Exit Enumeration")
* Axtor implements Controlled-Node Splitting and can cope with
irreducible control-flow.
(http://cardit.et.tudelft.nl/MOVE/papers/cc96.ps)
* Axtor translates switches to cascading
2012 Jul 10
4
[LLVMdev] New backend
Hello,
> You might grab some information from
> http://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf
> and around.
On Page 56 it says:
Maybe it’s a good idea to add ‘stub’ backend to the tree
Are there any plans to this?
I'd like to see a 'stub' backend in the llvm-tree (or somewhere else).
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2015 Mar 14
2
[LLVMdev] Add a backend
Is there documentation somewhere about exactly what the function is
supposed to do, or do I have to figure it out from existing examples?
On Sat, Mar 14, 2015 at 12:13 AM, Anton Korobeynikov <
anton at korobeynikov.info> wrote:
> You have to provide this function and initialize the whole MC
> infrastructure.
>
> See e.g. lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
>
>
2012 Jul 12
2
[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations
Hi Micah,
> We have a very similar setup with the AMDIL backend(some operations support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand.
thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer