similar to: [LLVMdev] help with tablegen

David Greene <dag at cray.com> writes: > I'm asking because I'm having some trouble converting some AVX patterns > over to the new system. I'm getting this error from tblgen: > > VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64

I have a few questions about the new vector shuffle matching code in the x86 .td files. It's a big improvement over the old system and provides the context that code generation for AVX needs. This is great! I'm asking because I'm having some trouble converting some AVX patterns over to the new system. I'm getting this error from tblgen: VyPERM2F128PDirrmi: (set:isVoid

On Thu, Aug 5, 2010 at 3:11 PM, David A. Greene <greened at obbligato.org> wrote: > David Greene <dag at cray.com> writes: > >> I'm asking because I'm having some trouble converting some AVX patterns >> over to the new system.  I'm getting this error from tblgen: >> >> VyPERM2F128PDirrmi:   (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64

Can someone explain why TableGen can't figure this out? VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32 (bitconvert:isInt (ld:v4i32 addr:iPTR:$src)<<P:Predicate_memop>>))) llvm/tblgen: In VCVTDQ2PS128rm: Could not infer all types in pattern! The pattern as written looks like this: [(set VR128:$dst, (v4f32 (sint_to_fp (bc_memopv4i32 addr:$src))))] I'm

How is bc_memopv4i32 defined? The bitconvert in the tablegen output is marked isInt, which means it's the node that didn't get inferred. Dan On Jun 4, 2009, at 1:06 PM, David Greene wrote: > Can someone explain why TableGen can't figure this out? > > VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32 > (bitconvert:isInt (ld:v4i32

On 1/15/2016 2:57 PM, Phil Tomson wrote: > > > I see the following in my SelectCode (in XSTGGenDGISel.inc): > > > /*2235*/ OPC_SwitchOpcode /*2 cases */, 27, > TARGET_VAL(XSTGISD::ADDR_NORMAL),// ->2266 > /*2239*/ OPC_RecordChild0, // #1 = $addr > /*2240*/ OPC_MoveChild, 0, > /*2242*/ OPC_CheckOpcode,

Hello Chris The general concept is to replace void with {}. Void is a weird type in >> that it is only allowed as the return value of functions and as the type of >> instructions like store. It seems better (though also not particularly >> high priority) to eliminate it to make the type system more consistent. >> > MVT::isVoid and Type::VoidTyID (getVoidTy) have

llvm[3]: Building X86.td register information header with tblgen Included from /usr/home/llvm/obj/../lib/Target/X86/X86.td:100: Included from /usr/home/llvm/obj/../lib/Target/X86/X86InstrInfo.td:2431: Parsing /usr/home/llvm/obj/../lib/Target/X86/X86InstrSSE.td:287: Invalid def 'int_x86_sse2_add_sd'! gmake[3]: *** [/usr/home/llvm/obj/lib/Target/X86/Debug/X86GenRegisterInfo.h.inc.tmp]

Hi, I've been hitting my head to wall two days now. This is practically my first contact with InstrInfo.td files. Is there any tutorial how to make this kind of stuff? Or should I just keep on studying Sparc and other backends? So I added new intrinsic to llvm/include/llvm/TCEInstrinsics.td: def int_tce_customop : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_vararg_ty], [],

Devang, I see the cause for confusion. Your message from this morning was specifically referring to this assert: Assertion `ExtVNI == VNI && "Unexpected existing value number"' failed. That assertion was fixed in the r144547. The PR shows this assert: Assertion failed: (isMetadata() && "Wrong MachineOperand accessor"), function Bisect fails until the

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let

Can anyone puzzle out what tblgen is trying to tell me here? VR256:v32i8:$src MD0.VMOVDQA_256mr: (st:isVoid VR256:v32i8:$src, addr:iPTR: $dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>> /ptmp/dag/universal_build/debug/DEFAULT/llvm/tblgen: In MD0.VMOVDQA_256mr: Type inference contradiction found in node! I don't see any

The AVX saga continues. I am attempting to write a pattern for VEXTRACTF128 but am having some problems. My attempt looks something like this: defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg, MRMDestMem, "extractf128", undef, X86f32, X86i32i8, // rr [(set VR128:$dst,

Hello, LLVM's intrinsic overloading mechanism does not currently support overloading on pointer types. Patches to implement this would be welcome. Dan On May 7, 2008, at 9:25 AM, aditya vishnubhotla wrote: > Hi, > I tried creating intrinsics which are to be > placeholders for a set of instructions (actually a section of a > basic block) to be executed elsewhere(for e.g. in

<table cellspacing='0' cellpadding='0' border='0' ><tr><td style='font: inherit;'>Hi,<br>I tried creating intrinsics which are to be<br>placeholders for a set of instructions (actually a section of a basic block) to be executed elsewhere(for e.g. in HW).<br>These intrinsics are to take care of the data dependencies of the set of

On Tuesday 24 March 2009 10:43, Chris Lattner wrote: > On Mar 23, 2009, at 5:56 PM, David Greene wrote: > > Is it legal to do something like a !strconcat on a non-string > > entity? That > > is, is there some operation that will let me do this (replace > > SOME_CONCAT with > > an appropriate operator): > > I don't get it, can you try a simpler example on

On Wed, Dec 2, 2009 at 3:46 PM, David Greene <dag at cray.com> wrote: > The AVX saga continues. > > I am attempting to write a pattern for VEXTRACTF128 but am having some > problems.  My attempt looks something like this: > > defm EXTRACTF128 : avx_fp_extract_vector_osta_node_mri_256<0x19, MRMDestReg, >                      MRMDestMem, "extractf128", undef,

On Apr 23, 2012, at 5:57 AM, Lyu Mitnick wrote: > Hello Chris > >> The general concept is to replace void with {}. Void is a weird type in that it is only allowed as the return value of functions and as the type of instructions like store. It seems better (though also not particularly high priority) to eliminate it to make the type system more consistent. > > MVT::isVoid

Hi, In my experiments, I need to disable several linking optimizations. However, bzip2, vortex and eon failed if "-disable-opt" was passed to gccld. I tried the out-of-box llvm and the building process provided by llvm-test. The same problem was observed, when I specified EXTRA_LINKTIME_OPT_FLAGS = -disable-opt on Makefile.program and simplied typed "make" under

Attached is a working patch set for llvm to be able to emit arm64 (currently as triple aarch64-apple-ios) mach-o object files, in case someone is interested. I'm not sure if the llvm maintainers want the patch given the previous message that there's going to be an official patch set from apple to support this, but here is mine. What works (tested on an iPhone 5S): * objc strings,