Displaying 20 results from an estimated 5000 matches similar to: "[LLVMdev] WG: TableGen: NumResults <= 1 restriction"
2009 May 13
2
[LLVMdev] TableGen: NumResults <= 1 restriction
Hi all,
i'm working atm on a backend for a processor architecture that is
capable of storing the carry flag of ADDC in an 1-bit register class. So
I tried to lower the ADDC instruction to generate two register values as
result. On the tablegen description of the instruction i came across the
tablegen restriction that only one output result of one instruction is
possible:
2009 May 13
0
[LLVMdev] TableGen: NumResults <= 1 restriction
On May 13, 2009, at 7:22 AM, Stripf, Timo wrote:
> Hi all,
>
> i’m working atm on a backend for a processor architecture that is
> capable of storing the carry flag of ADDC in an 1-bit register
> class. So I tried to lower the ADDC instruction to generate two
> register values as result. On the tablegen description of the
> instruction i came across the tablegen
2009 May 13
0
[LLVMdev] DataStructure Analysis ds-aa can not stop when passing mysqld
Quoting hc2428 at columbia.edu:
Dear staff,
Here is the bc file.
Heming
> Quoting Chris Lattner <clattner at apple.com>:
>
> Dear staff,
> I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12
> statically (compile all libraries statically to the executable) and
> got the bc file, named it as mysqld.bc3.
> I use the command to pass:
>
> opt
2009 May 13
4
[LLVMdev] DataStructure Analysis ds-aa can not stop when passing mysqld
Quoting Chris Lattner <clattner at apple.com>:
Dear staff,
I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12
statically (compile all libraries statically to the executable) and
got the bc file, named it as mysqld.bc3.
I use the command to pass:
opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa
mysqld.bc3 -print-alias-sets -disable-output
2009 May 18
0
[LLVMdev] DataStructure Analysis ds-aa can not stop when passing mysqld
On Wed, May 13, 2009 at 1:36 PM, <hc2428 at columbia.edu> wrote:
> Quoting Chris Lattner <clattner at apple.com>:
>
> Dear staff,
> I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12
> statically (compile all libraries statically to the executable) and
> got the bc file, named it as mysqld.bc3.
> I use the command to pass:
>
> opt -load
2009 Aug 11
0
[LLVMdev] Bug in optimization pass related to strcmp and big endian back-ends
On Tue, Aug 11, 2009 at 1:13 AM, Stripf,
Timo<Timo.Stripf at itiv.uni-karlsruhe.de> wrote:
> On little endian machines the code works correct but on big endian %lhsv
> must be compared against 73 << 8.
If llvm-gcc thinks it's compiling for a little-endian target, the
optimizers will assume the target is little-endian... what are you
trying to do?
-Eli
2009 Aug 11
2
[LLVMdev] Bug in optimization pass related to strcmp and big endian back-ends
Hi all,
i'm working on a LLVM back-end right now and i think I found a bug in an
optimization pass. When compiling the following code using llvm-gcc (the
current 2.5 release) with -O2
int main(int argc, char** argv) {
char* pStr = "I" + (argc > 100);
printf("%d\n", strcmp(pStr, "I") == 0);
}
the strcmp
2009 Aug 11
5
[LLVMdev] Bug in optimization pass related to strcmp and bigendian back-ends
I thought the LLVM IR is target independent and that "llvm-gcc -c -emit-llvm -O2" produces target independent code.
I'm working on a back-end and use llvm-gcc to first generate the bc file. Afterwards I use llc including the new back-end to produce the assembler file.
-Timo
-----Ursprüngliche Nachricht-----
Von: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
2012 Sep 25
2
[LLVMdev] Publication: Two LLVM-related papers
Hi,
i've two papers that could be listed on the LLVM publication page. http://www.llvm.org/pubs/
The first paper describes an architecture description language and LLVM back-end generation out of an ADL. The second paper describes a cluster VLIW back-end for LLVM 2.9, just before this VLIW initiative started for LLVM.
Kind regards,
Timo Stripf
Stripf, T.; Koenig, R.; Becker, J.; , "A
2009 Aug 23
4
[LLVMdev] Problems with DAG Combiner
Hi all,
i'm writing an back-end for a new research processor architecture and
have problems with the DAG Combiner. The processor architecture supports
i1 and i32 registers. 1-bit registers are mainly used as comparison
result but basic operations like OR are not possible between i1
registers. So I wrote custom lowering for i1 OR operations and replaced
it by (trunc (or (aext x), (aext
2009 Aug 28
1
[LLVMdev] Problems with DAG Combiner
I converted now my back-end with legal i1 lowering to the 2.6 branch and my original problem with the DAG combiner didn't occur any more and seems to be fixed. setOperationAction(ISD::OR, MVT::i1, Promote) also works fine for logical operations.
> What is your SetCCResultType now?
I changed SetCCResultType to return MVT::i1 type.
> Can you compile the CodeGen/Blackfin/basic-i1.ll
2009 Aug 23
2
[LLVMdev] Problems with DAG Combiner
Hi Jakob,
I forget to mention that I'm working atm on the old 2.5 release code base and not on the svn. So I don't know if the problem still exists. I'm going to test it now.
> The Blackfin DSP can do simple i1 operations with the CC flag and
> status bits. Initially I also marked i1 as a legal type, but it caused
> a lot of problems. Now I pretend that the CC register
2009 Aug 24
0
[LLVMdev] Problems with DAG Combiner
On 24/08/2009, at 01.19, Stripf, Timo wrote:
>
> I had also a lot of problems to get the i1 operations working. E.g.
> I had to override the getSetCCResultType to get is working and for
> ADDE/ADDC the i1 target registers are hardcoded.
What is your SetCCResultType now?
Can you compile the CodeGen/Blackfin/basic-i1.ll test case? I never
got that one working with legal i1. The
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I wanted to inform that I fixed the bug from the previous email.
The main reason for the bug was that I thought that the SDNode masked_gather is
returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult
to follow, error: "Assertion `New->getNumTypes() == 1").
masked_gather returns 2 values because:
// SDTypeProfile -
2013 Jan 07
0
[LLVMdev] TableGen patterns with multiple outputs
On Jan 4, 2013, at 9:52 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
> Are multi-output patterns in TableGen supposed to work, or is that a known limitation in the current implementation?
It is a known limitation. You have to write C++ code to match patterns with multiple outputs.
>
> If I have TableGen code like the following...
>
> 1242 def SDTTestNode
2013 Jan 04
2
[LLVMdev] TableGen patterns with multiple outputs
Are multi-output patterns in TableGen supposed to work, or is that a known
limitation in the current implementation?
If I have TableGen code like the following...
1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
1244
1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0,
2013 Jan 07
0
[LLVMdev] TableGen patterns with multiple outputs
It has been something we've talked about for years, but I'm not aware of anyone working on it right now.
On Jan 6, 2013, at 5:34 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote:
> Thanks for the info. Is this on someone's list of things to do?
>
>
> On Sun, Jan 6, 2013 at 7:41 PM, Bob Wilson <bob.wilson at apple.com> wrote:
>
> On Jan 4,
2013 Jan 07
2
[LLVMdev] TableGen patterns with multiple outputs
Thanks for the info. Is this on someone's list of things to do?
On Sun, Jan 6, 2013 at 7:41 PM, Bob Wilson <bob.wilson at apple.com> wrote:
>
> On Jan 4, 2013, at 9:52 AM, Justin Holewinski <justin.holewinski at gmail.com>
> wrote:
>
> Are multi-output patterns in TableGen supposed to work, or is that a known
> limitation in the current implementation?
>
2019 Nov 19
2
Question about physical registers in ISel
Hi all,
I need to figure out why InstrEmitter::EmitMachineNode assumes that when
the number of outputs of a MachineSDNode is greater than the number of defs
in the corresponding MCInstrDesc, the outputs in the difference will be
placed into physical registers as opposed to virtual registers.
The specific line in question is:
bool HasPhysRegOuts = NumResults > NumDefs &&
2006 Feb 07
0
WG: AW: WG: proxyarp <--> OpenSwan VPN/Internet
I´ve figured out the following.
I am able to sftp from shorewall 2.4.2 left vpn gateway x.x.x.14 (DMZ) to
shorewall 2.4.1 fw x.x.x.11 with /etc/shorewall/proxyarp
x.x.x.14 eth2 eth0 No
very well. That´s not through a tunnel (of course a ssh tunnel, but no vpn)
but with public ip x.x.x.14 to x.x.x.11
If I try to sftp through the fw to the public internet I have the same