similar to: [LLVMdev] TableGen: NumResults <= 1 restriction

On May 13, 2009, at 7:22 AM, Stripf, Timo wrote: > Hi all, > > i’m working atm on a backend for a processor architecture that is > capable of storing the carry flag of ADDC in an 1-bit register > class. So I tried to lower the ADDC instruction to generate two > register values as result. On the tablegen description of the > instruction i came across the tablegen

Quoting Chris Lattner <clattner at apple.com>: Dear staff, I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12 statically (compile all libraries statically to the executable) and got the bc file, named it as mysqld.bc3. I use the command to pass: opt -load <poolalloc install dir>/lib/libLLVMDataStructure.so -ds-aa mysqld.bc3 -print-alias-sets -disable-output

Quoting hc2428 at columbia.edu: Dear staff, Here is the bc file. Heming > Quoting Chris Lattner <clattner at apple.com>: > > Dear staff, > I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12 > statically (compile all libraries statically to the executable) and > got the bc file, named it as mysqld.bc3. > I use the command to pass: > > opt

On Wed, May 13, 2009 at 1:36 PM, <hc2428 at columbia.edu> wrote: > Quoting Chris Lattner <clattner at apple.com>: > > Dear staff, >     I am using the ds-aa to pass mysqld. I compile mysqld 4.0.12 > statically (compile all libraries statically to the executable) and > got the bc file, named it as mysqld.bc3. >     I use the command to pass: > > opt -load

Hi all, i'm working atm on a backend for a processor architecture that is capable of storing the carry flag of ADDC in an 1-bit register class. So I tried to lower the ADDC instruction to generate two register values as result. On the tablegen description of the instruction i came across the tablegen restriction that only one output result of one instruction is possible:

Hi all, i'm working on a LLVM back-end right now and i think I found a bug in an optimization pass. When compiling the following code using llvm-gcc (the current 2.5 release) with -O2 int main(int argc, char** argv) { char* pStr = "I" + (argc > 100); printf("%d\n", strcmp(pStr, "I") == 0); } the strcmp

On Tue, Aug 11, 2009 at 1:13 AM, Stripf, Timo<Timo.Stripf at itiv.uni-karlsruhe.de> wrote: > On little endian machines the code works correct but on big endian %lhsv > must be compared against 73 << 8. If llvm-gcc thinks it's compiling for a little-endian target, the optimizers will assume the target is little-endian... what are you trying to do? -Eli

Hi, I'm writing a ModulePass that needs critical edges split up. I have the statement AU.addRequiredID(BreakCriticalEdgesID); in my getAnalysisUsage() but the pass never gets executed. I guess I have to request pass execution for each function, but I can't get behind how to do that, since there is no analysis group for that kind of transformation. Thanks, Andi

Hi, i've two papers that could be listed on the LLVM publication page. http://www.llvm.org/pubs/ The first paper describes an architecture description language and LLVM back-end generation out of an ADL. The second paper describes a cluster VLIW back-end for LLVM 2.9, just before this VLIW initiative started for LLVM. Kind regards, Timo Stripf Stripf, T.; Koenig, R.; Becker, J.; , "A

I thought the LLVM IR is target independent and that "llvm-gcc -c -emit-llvm -O2" produces target independent code. I'm working on a back-end and use llvm-gcc to first generate the bc file. Afterwards I use llc including the new back-end to produce the assembler file. -Timo -----Ursprüngliche Nachricht----- Von: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at

Hi all, i'm writing an back-end for a new research processor architecture and have problems with the DAG Combiner. The processor architecture supports i1 and i32 registers. 1-bit registers are mainly used as comparison result but basic operations like OR are not possible between i1 registers. So I wrote custom lowering for i1 OR operations and replaced it by (trunc (or (aext x), (aext

Dear list, I am facing a problem in my statistical analyses on R. My experiments are about plants, I record there growth after each cutting (every 3 weeks). 'BC' is for the plant, and '1' to '5' is the time of cutting and recording. The data and R script are : "" BourdCoup <- c(21, 7.2, 9.2, 0, 8.52, 14.7, 8.31, 6.2, 127.05, 115.2, 100.7, 24, 162.64, 136.8,

I am getting the following error when i am trying to generate the code. In the optimization pass I have inserted some calls llvm.annotation.i32 class to provide indentification tags to loops to be used in subsequent passes. Codegen is complaining about these annotations. llc -march=c ham1_seq.bc3 Error: Code generator does not support intrinsic function 'llvm.annotation.i32'! llc

Hi all, I need to figure out why InstrEmitter::EmitMachineNode assumes that when the number of outputs of a MachineSDNode is greater than the number of defs in the corresponding MCInstrDesc, the outputs in the difference will be placed into physical registers as opposed to virtual registers. The specific line in question is: bool HasPhysRegOuts = NumResults > NumDefs &&

On Oct 25, 2011, at 1:59 AM, Stripf, Timo wrote: > Hi all, > >> Ok, so in your proposal a bundle is just a special MachineInstr? That sounds good. How are the MachineInstr's embedded inside a bundle? How are the cumulative operands, implicit register defs and uses represented? > > I attached the packing and unpacking pass I used within my backend. In my solution multiple

Hi Jakob, I forget to mention that I'm working atm on the old 2.5 release code base and not on the svn. So I don't know if the problem still exists. I'm going to test it now. > The Blackfin DSP can do simple i1 operations with the CC flag and > status bits. Initially I also marked i1 as a legal type, but it caused > a lot of problems. Now I pretend that the CC register

On 24/08/2009, at 01.19, Stripf, Timo wrote: > > I had also a lot of problems to get the i1 operations working. E.g. > I had to override the getSetCCResultType to get is working and for > ADDE/ADDC the i1 target registers are hardcoded. What is your SetCCResultType now? Can you compile the CodeGen/Blackfin/basic-i1.ll test case? I never got that one working with legal i1. The

Hi Quentin, Thanks, that explanation makes sense. I can see that in a normal register machine, implicitly defs must be physical registers. In a stack machine like WebAssembly, though, implicit defs are known to be pushed onto the value stack just like any other defs. Slots on the value stack are represented by virtual registers until stackification, so for WebAssembly we do need the implicit defs

Hello, I've only had experience with PostgreSQL sofar, but have now to install MySQL (and WordPress) on a CentOS 6.4 /64 bit server. I have installed the mysql-5.1.69-1.el6_4.x86_64 package and executed the following commands: # chkconfig mysqld on # service mysqld start # /usr/bin/mysqladmin -u root password 'xxxxx' # /usr/bin/mysql_secure_installation Then I've noticed that

Hi Timo, your approach is quite similar to the one in the patch I sent a couple of weeks ago. I also have the Bundle (derivate from MachineInstruction so I call it "MachineInstructionBundle") and pack/unpack so RegAlloc works on the bundles… I really think this is the way to incorporate VLIW support to LLVM. I guess a need for some of this to make to LLVM trunk is to have a backend