similar to: [LLVMdev] Prevent node from being combined

On 5/16/2013 11:17 AM, Jakob Stoklund Olesen wrote: > > Would this TRI function solve your problem? >[...] > /// > /// Covering = getCoveringLanes(); > /// MaskA = getSubRegIndexLaneMask(SubA); > /// MaskB = getSubRegIndexLaneMask(SubB); > /// > /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by > /// SubB.

Manjunath, I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov. For example, Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask. So I have dst, src0, src1, imm1, imm2 And I have my asm look similar to: Add dst, src0.imm1, src1.imm2 and then in the asm

Dan, Thanks a lot. Using a modifier in the assembly string works for this case. I am trying to solve a related problem. I am trying to print out a set of "mov" ops for the vector_shuffle node. Since the source of the "mov" is from one of the sources to vector_shuffle, depending on the mask, I am not sure what assembly string to emit. For example, if I have d <-

On May 16, 2013, at 8:13 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are

? Fri, 16 Aug 2024 11:32:58 +0200 <sibylle.stoeckli at gmx.ch> ?????: > # values and mask r1 > r1 <- getValues(r1) > mask1 <- is.na(r1) > # Do the same for r2 > r2 <- getValues(r2_resampled) > mask2 <- is.na(r2) > > # Combine the masks > all.equal(r1[!(mask1 & mask2)], r2[!(mask1 & mask2)]) Let's consider a more tangible example: # The

Cool thanks # values and mask r1 r1 <- getValues(r1) mask1 <- is.na(r1) # Do the same for r2 r2 <- getValues(r2_resampled) mask2 <- is.na(r2) # Combine the masks all.equal(r1[!(mask1 & mask2)], r2[!(mask1 & mask2)]) output > all.equal(r1[!(mask1 & mask2)], r2[!(mask1 & mask2)]) [1] "'is.NA' value mismatch: 389 in current 56989152 in target"

The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are D0. The context here is an attempt to coalesce multiple loads/stores into fewer loads/stores

Dear Ivan Thanks a lot for this very nice example. Is it true that all.equal just compares y values? Based on this help here I think so and the value I got is the difference for the y-values. https://www.statology.org/all-equal-function-r/ However, here I see x and y testing? https://www.rdocumentation.org/packages/base/versions/3.6.2/topics/all.equal I am actually interested in the x values

I want to add a set of "properties" to each instruction in my instruction set, and want to be able to query that in my machine-specific optimizations. My Insts.td file looks as follows : class InstProperty; def propX : InstProperty; def propY : InstProperty; def propZ : InstProperty; class myInst<..., list<InstProperty> props> : Instruction { ... ...

Manjunath, I asked this question recently, but instead of telling you to search the archive I'm going to take it as a chance to recall how to do it (because I'll do so anyway and even telling tablegen to use an enum for instructions is not as trivial to do as you might think : ) I wrote it up in the wiki at http://wiki.llvm.org/HowTo:_Add_arbitrary_properties_to_instructions Regards,

"Is it true that all.equal just compares y values?" The following may be a bit more than you may have wanted, but I hope it is nevertheless useful. The first place you should go to for questions like this is the Help system, not here, i.e. ?all.equal When you do this, you will find that all.equal() is a so-called S3 generic function, which, among other things, means that it works

Hi LLVM, I ran into a case where RegAlloc would insert a spill across instruction that had same register for output operand and implicit-def. The effect this had was that spill code would immediately overwrite the output result. Is this the expected result of setting up MyInst this way? In other words, does RegAlloc know to not insert spill in case it sees that output reg is same as one of

Hi Quentin, MyInst is a custom instruction that has implicit-defs of fixed registers. The implicit-defs are seen at the end of Instruction Selection. I'd like to add a report, but I am working on an out-of-tree backend based on 7.0. I can try to help reduce the testcase down. Filed https://bugs.llvm.org/show_bug.cgi?id=41790 Regards, Kevin On 2019-05-07 3:45 p.m., Quentin Colombet wrote:

?? The OP's original problem is that the all.equal method for raster objects (raster:::all.equal.raster), which is a wrapper around the compareRaster() function, compares a bunch of different properties of rasters (extent, resolution, values, etc.) and only returns a single overall logical (TRUE/FALSE) value. OP wanted to see the magnitude of the difference (as you could get for more

Ah...I see. Perhaps, then, the maintainer should be contacted, as the desired functionality seems similar to that provided in other all.equal methods. I realize that this may often not elicit a (prompt) response. -- Bert On Sun, Aug 18, 2024 at 11:50?AM Ben Bolker <bbolker at gmail.com> wrote: > > The OP's original problem is that the all.equal method for raster >

Also some missing _src()s and cosmetic changes. --- src/gallium/programs/galliumut/Makefile | 5 + .../programs/galliumut/gen_uureg_opcodes.sh | 29 +++ src/gallium/programs/galliumut/uureg.h | 196 ++++---------------- 3 files changed, 71 insertions(+), 159 deletions(-) create mode 100644 src/gallium/programs/galliumut/gen_uureg_opcodes.sh diff --git

It seems to me that LLVM sub-register is not for the following hardware architecture. All instructions of a hardware are vector instructions. All registers contains 4 32-bit FP sub-registers. They are called r0.x, r0.y, r0.z, r0.w. Most instructions write more than one elements in this way: mul r0.xyw, r1, r2 add r0.z, r3, r4 sub r5, r0, r1 Notice that the four elements of r0 are written

? Fri, 16 Aug 2024 10:35:35 +0200 <sibylle.stoeckli at gmx.ch> ?????: > what do you mean by use is.na() in getValues(). So I need to call > getValues a second time? Not necessarily, but it's one of the options. I was thinking along the lines of: values1 <- getValues(r1) mask1 <- is.na(values1) # Do the same for r2 # Combine the masks all.equal(values1[!combined_mask],

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =

On Mon, Jan 5, 2009 at 2:32 PM, Alex <alex.lavoro.propio at gmail.com> wrote: > In .td file, if the pattern to match the DAG is: > > (vector_shuffle (mul build_vector, build_vector)) > > is it possible to return 'mul' (SDNode*) instead of returning the first > 'vector_shuffle'? > > It seems to me that the default instruction selector can only return