similar to: [LLVMdev] C-to-verilog

First, some logistical information. The conference will be held at the San Jose Hilton. I've updated the webpage with the exact location. During registration (coming very soon!) you will have the opportunity to book a hotel room directly through that process (and get the reduced rate). Now, I'm pleased to announce the tentative agenda for the 2010 LLVM Developers' Meeting: LLDB -

Hi, I am working on to implement Scilab codes to FPGA format i.e, a similar kind of c to vhdl by trident compiler.Is there anybody working on this? Regards Manas Das Research Assistant IIT-Bombay -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120919/7eac124e/attachment.html>

Hi Chris, Wojciech, Data Dependence Analysis is great. I am sure it would help the loop optimizations effort that Dr. Adve mentioned last month. After we have DDA we can implement software pipelining* (modulo scheduler). Chris, would you accept a software pipelining transformation as a pass or would you want it as part of the different backends ? Nadav Rotem *

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is

Yes I know, I'm having problems with these tests because they violate the documentation. :) Micah From: Nadav Rotem [mailto:nrotem at apple.com] Sent: Wednesday, October 10, 2012 11:52 AM To: Villmow, Micah Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Inconsistency in the LLVM docs Hi Micah, We need to fix the documentation here. We want to be able to convert vectors of integers to

On Sat, Mar 2, 2019 at 12:58 AM Fedor Sergeev <fedor.sergeev at azul.com> wrote: > > > On 3/2/19 2:38 AM, Hiroshi Yamauchi wrote: > > Here's a sketch of the proposed approach for just one pass (but imagine > more) > > https://reviews.llvm.org/D58845 > > On Fri, Mar 1, 2019 at 12:54 PM Fedor Sergeev via llvm-dev < > llvm-dev at lists.llvm.org>

Here's a sketch of the proposed approach for just one pass (but imagine more) https://reviews.llvm.org/D58845 On Fri, Mar 1, 2019 at 12:54 PM Fedor Sergeev via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/28/19 12:47 AM, Hiroshi Yamauchi via llvm-dev wrote: > > Hi all, > > To implement more profile-guided optimizations, we’d like to use > ProfileSummaryInfo

On 3/14/19 2:04 AM, Hiroshi Yamauchi wrote: > > > On Wed, Mar 13, 2019 at 2:37 PM Fedor Sergeev <fedor.sergeev at azul.com > <mailto:fedor.sergeev at azul.com>> wrote: > >> >> - Add a new proxy ModuleAnalysisManagerLoopProxy for a loop pass >> to be able to get to the ModuleAnalysisManager in one step and >> PSI through it. >

On 3/4/19 10:49 PM, Hiroshi Yamauchi wrote: > > > On Mon, Mar 4, 2019 at 10:55 AM Hiroshi Yamauchi <yamauchi at google.com > <mailto:yamauchi at google.com>> wrote: > > > > On Sat, Mar 2, 2019 at 12:58 AM Fedor Sergeev > <fedor.sergeev at azul.com <mailto:fedor.sergeev at azul.com>> wrote: > > > > On 3/2/19 2:38 AM,

Hi all, To implement more profile-guided optimizations, we’d like to use ProfileSummaryInfo (PSI) and BlockFrequencyInfo (BFI) from more passes of various types, under the new pass manager. The following is what we came up with. Would appreciate feedback. Thanks. Issue It’s not obvious (to me) how to best do this, given that we cannot request an outer-scope analysis result from an inner-scope

Overall seems fine to me. On 3/11/19 8:12 PM, Hiroshi Yamauchi wrote: > Here's a revised approach based on the discussion: > > - Cache PSI right after the profile summary in the IR is written in > the pass pipeline. This would avoid the need to insert > RequireAnalysisPass for PSI before each non-module pass that needs it. > PSI can be technically invalidated but unlikely

I'd might think about that, I have created quite a few Python bindings and, oddly enough, do enjoy it, probably just because of how easy boost::python makes it (I have always manually done it directly using that, but because of the sheer size of LLVM I may use a code generator to generate the basics, and yes I know how to manually create python C modules without any binder, but boost::python

TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never

Luke Kenneth Casson Leighton wrote: > i was just writing this: > http://www.gp32x.com/board/index.php?/topic/60228-replicating-the-success-of-the-openpandora-discussion-v20/ > > when something that just occurred to me, half way through, and i would > greatly appreciate some help evaluating whether it's feasible. > > put these together: >

On 02/07/2013 11:49 PM, Nadav Rotem wrote: > > On Feb 7, 2013, at 10:55 AM, Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> wrote: > >> Hi Nadav, >> >> On 02/07/2013 07:46 PM, Nadav Rotem wrote: >>> Pekka suggested that we add two kind of metadata: llvm.loop.parallel >>> (attached to each loop latch) and llvm.mem.parallel (attached to each

Some thoughts: o To determine the VF for a loop with mixed data sizes, choosing the smallest ensures each vector register used is full, choosing the largest will minimize the number of vector registers used. Which one’s better, or some size in between, depends on the target’s costs for the vector operations, availability of registers and possibly control/memory divergence and trip count. “This is

Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it

On Sun, 15 Apr 2012 20:02:36 +0000 "Rotem, Nadav" <nadav.rotem at intel.com> wrote: > Hi Hal! > > This is great! Vector-selects are always profitable compared to > scalar selects. They are even emulated using a few Xor/And/Or > instructions on platforms that don't have a native 'blend' support. > > Vector-geps on the other hand are only useful

Hi James, Having not worked on this for circa one year I've gone and refreshed my memory. We have a pretty capable implementation of swing modulo scheduling downstream, distinct from the MachinePipeliner implementation. Historically, MachinePipeliner had very tight coupling between the finding of a suitable schedule and emitting the code that adheres to that schedule. I spent quite a bit of