similar to: [LLVMdev] Custom lowering ADDE?

Any idea how to handle "adde" nodes for processors that do not have an "add with carry" instruction? In our case, we rely on "carry test" and "increment" instrunctions. Any reference to a similiar existing LLVM target will be helpful.. TIA, Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Nov 10, 2008, at 9:51 AM, sanjiv gupta wrote: > Ours is an accumulator based architecture. > > So one operand of ADD/SUB operations is in REG (accumulator) and the > other one is in Memory. The result can be left either in REG or > memory. > > The LLVM DAG for such operations expect both operands in REG. > > for example: > char a, b, c, d, e; > a = (b - c) +

Ours is an accumulator based architecture. So one operand of ADD/SUB operations is in REG (accumulator) and the other one is in Memory. The result can be left either in REG or memory. The LLVM DAG for such operations expect both operands in REG. for example: char a, b, c, d, e; a = (b - c) + (d - e); generates addc:i8 (subc:i8(b,c), subc:i8(d,e)) Looks like we need to custom lower addc

On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: > On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: > > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && > > "Invalid operand expansion"); > > > > LOAD node has two values but the assertion checks N->getNumValues() == 1 >

On Tue, Aug 19, 2008 at 8:07 AM, sanjiv gupta <sanjiv.gupta at microchip.com> wrote: > On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: >> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: >> > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && >> > "Invalid operand

thanks Evan, I have just started writing td files. Any ideas how do I describe instructions for an accumulator based machine. The other pecularity is that we do not want to have any software stack. So the instructions like load and store have no meanings. In that case, how do I lower instructions that operate on stack frame? TIA, Sanjiv On 11/26/07, Evan Cheng <evan.cheng at apple.com>

On Mon, 2009-10-05 at 16:54 -0700, Eli Friedman wrote: > On Mon, Oct 5, 2009 at 11:11 AM, Sanjiv Gupta > <sanjiv.gupta at microchip.com> wrote: > > Sanjiv Gupta wrote: > >> Sanjiv Gupta wrote: > >> > >>> Duncan Sands wrote: > >>> > >>> > >>>> Hi Sanjiv, I think a lot of the softening code assumes you are

On Nov 24, 2007, at 7:28 PM, Sanjiv Gupta wrote: > Could anybody guide me what information do I need to know about my > target in order to provide the target lowering info to the llvm DAG > generator? We do not have any fixed registers for argument passing. > Everything including the formal and actual arguments will take part in > a global interprocedural regalloc. You don't

Mikhail Glushenkov wrote: > Hi Sanjiv, > > 2009/6/18 Sanjiv Gupta <sanjiv.gupta at microchip.com>: > >> Hi Mikhail, >> Thanks for your wonderful help so far. I have few more questions to ask: >> >> How do I modify the driver to pick tools from where the driver itself >> resides, rather than from the PATH? >> Do I need to write some C++ code

On Wed, Jul 15, 2009 at 7:29 PM, sanjiv gupta<sanjiv.gupta at microchip.com> wrote: > On Wed, 2009-07-15 at 10:37 -0700, Devang Patel wrote: >> On Wed, Jul 15, 2009 at 9:32 AM, sanjiv gupta<sanjiv.gupta at microchip.com> wrote: >> > Consider the example command line below >> > >> > $ llvm-ld -disable-opt hello.bc -l std -o hello.out >> >

Dear All, I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example: shl i32 %a , 2 => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )

On Mon, Oct 5, 2009 at 11:11 AM, Sanjiv Gupta <sanjiv.gupta at microchip.com> wrote: > Sanjiv Gupta wrote: >> Sanjiv Gupta wrote: >> >>> Duncan Sands wrote: >>> >>> >>>> Hi Sanjiv, I think a lot of the softening code assumes you are dealing >>>> with float (32 bits).  So it's not just a matter of changing the libcall

Sanjiv Gupta wrote: > Sanjiv Gupta wrote: > >> Duncan Sands wrote: >> >> >>> Hi Sanjiv, I think a lot of the softening code assumes you are dealing >>> with float (32 bits). So it's not just a matter of changing the libcall >>> return type. >>> >>> >>> >> Yes, we are dealing with 32-bits

On Wed, 2009-07-15 at 10:37 -0700, Devang Patel wrote: > On Wed, Jul 15, 2009 at 9:32 AM, sanjiv gupta<sanjiv.gupta at microchip.com> wrote: > > Consider the example command line below > > > > $ llvm-ld -disable-opt hello.bc -l std -o hello.out > > > > Why does -disable-opt links in all the bitcode from the libstd.so into > > hello.out? > > ...

My target doesn't support 64 bit arithmetic, so I'd like to supply definitions for adde/addc. The problem is I can't seem to figure out the magic. Here's an example of what I need to generate: # two i64s in r5/r6 and r7/r8 # result in r1/r2, carry in r3 # adde add r2, r6, r8 cmpltu r3, r2, r6 # compute carry # addc add r1, r5, r7 add r1, zero, r3 Is this

Mikhail Glushenkov wrote: > Hi, > > On Thu, Sep 10, 2009 at 8:01 PM, Sanjiv Gupta > <sanjiv.gupta at microchip.com> wrote: > >> Why do we need both 'conflict' and 'warning' ? >> > > 'warning' just prints a warning, 'conflict' is a fatal error. > > A better example would be something like: > > (warning (and

Hi Sanjiv, 2009/6/29 Sanjiv Gupta <sanjiv.gupta at microchip.com>: > I want to retrieve the value of argv[0] (which was passed to main function > of the driver) in PrependCustomizedPath. I've added a way to access argv[0] in hooks: http://thread.gmane.org/gmane.comp.compilers.llvm.cvs/50789 -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against

Hi Sanjiv, On Wed, Jul 1, 2009 at 7:02 PM, Sanjiv Gupta<sanjiv.gupta at microchip.com> wrote: > I found out the problem. Looks like I can not rely on argv[0] to contain the > full path of the executable always. Yeah, that's what I was thinking. > Can I rely on: > static Path GetMainExecutable(const char *argv0, void *MainAddr); Clang relies on it. According to

Mikhail Glushenkov wrote: > Hi Sanjiv, > > 2009/6/15 Sanjiv Gupta <sanjiv.gupta at microchip.com>: > >> Hi Mikhail, >> How do you build mcc16 executable? >> > > This should work: > > $ cd $LLVM_DIR/tools/llvmc/examples/mcc16 > $ make > > I configure llvm into a separate directory from source. When I do the steps you mentioned in

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I