similar to: [LLVMdev] Tablegen address space

I'm trying to write a store pattern that accepts both i32 and f32, however, when tablegen generates the code, it only generates the code for i32 only. def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; def MEM : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); } def global_st :

I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also,

I have a simple test case that my code generator handles fine when using optimizations, but when I disable optimizations, It turns into a sequence of instructions that I can't figure out what to setup to get it to generate the correct code. The instructions in question are: %tmp1 = load float* %test ; <float> [#uses=1] %conv = fpext float %tmp1 to double ;

Is there a way to tell LLVM to treat Boolean results as 32bit values instead of 1 bit values? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL:

I am attemping to figure out how to access the function names that are stored in a module so that I know which function I am currently in. I am attempting to write a backend that targets a language that only allows integer function names and I need to create mapping between the string and the integer. I've looked in the header files but I cannot determine how to extract the function

How do I determine what type of register(i.e. i32, f32, etc..) I am accessing from a MachineOperand? I.e. how do I get to the MVT struct, or equivalent information, from a MachineOperand object? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596

I have a tablegen string that I want to add a modifier to the registers that are being matched. For example a simple match on fneg: def FNEG : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins GPR:$src0), "mov $dst, $src0", [(set GPR:$dst, (fneg GPR:$src0))]>; I want to place a modifier directly after $src0 in the string so that no space is between the string and

Is there a way for tablegen to generate patterns for all the data types of a specific register class instead of just the first one? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was

That's how ISD::SETCC is specified. If you want to change that for your target, you should custom lower these nodes to target nodes. Then you can specify your own SDNode with your own SDTypeProfile. Evan On Oct 24, 2008, at 4:31 PM, Villmow, Micah wrote: > I am attempting to match setcc using tablegen w/ the following > patterns: > def FEQ : Instruction<(outs

On Sep 23, 2008, at 10:44 AM, Villmow, Micah wrote: > I’m trying to write a store pattern that accepts both i32 and f32, > however, when tablegen generates the code, it only generates the > code for i32 only. > > def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; > def MEM : Operand<i32> { > let PrintMethod = "printMemOperand";

I am having trouble trying to figure out two pieces of information from attempting to map arguments to registers. How do I determine, based on the argument name, which register the value is supposed to be assigned to? I can hard-coded it currently and it will be correct 100% of the time with the current set of assumptions, but I would rather determine it dynamically so that I can change my

Is there currently a way to have virtual register allocation information be saved across functions so that if I create a new virtual register in a function that it doesn't use a virtual register allocated in any previous function? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054

On Nov 18, 2008, at 11:24 AM, Villmow, Micah wrote: > Is there a way to tell LLVM to treat Boolean results as 32bit values > instead of 1 bit values? LLVM IR doesn't have a concept of C level booleans. What problem are you trying to solve? -Chris > > Thanks, > > Micah Villmow > Systems Engineer > Advanced Technology & Performance > Advanced Micro Devices

I am getting an assert on a bad legalization. Assertion failed: Result.getValueType() == Op.getValueType() && "Bad legalization!", file ..\..\lib\CodeGen\SelectionDAG\LegalizeDAG.cpp, line 3976 Can someone explain to me what this means in term of backend code generation, how it might be occurring, and possible ways to fix this? I don't see how the value type of an

As stated in an earlier email, I am working on getting break/continue to work correctly for my backend, but I ran into another issue with codegen and the CFG. It seems that code gen is not done based on the CFG, but rather on the block numbers, and the function call MachineFunction::RenumberBlocks doesn't renumber the blocks based on the CFG. So how can I modify the CFG so that when codegen

Is there a simple way to specify the relationship between two different register classes of various sizes and alignments as being legal to convert between them? I have my backend written up using a single register class for i32, i64, f32 and f64 types, however, because the type information is not propagated down to the machine instruction register level, it is not known to me how to determine

You can get to the MachineInstr from a MachineOperand. Then get to its TargetInstrDesc and TargetOperandInfo which has register class information. Evan On Sep 23, 2008, at 12:44 PM, Villmow, Micah wrote: > How do I determine what type of register(i.e. i32, f32, etc..) I am > accessing from a MachineOperand? I.e. how do I get to the MVT > struct, or equivalent information, from

How do I access the address qualifier from the store instruction. Given the following code: define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) nounwind { entry: %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm

When I setup my InstrFormat fields, I added some custom fields specific for my backend. How do I access these from inside LLVM? For example: class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMD"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let

Is there currently a way to use a pattern inside of another pattern? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 -------------- next part -------------- An HTML attachment was scrubbed... URL: