similar to: [LLVMdev] A case where llvm created different cfg for same code

Hi, > 7 for(i=0; i<j && i+j+1<N; i++) { > > 8 for(i=0; i<j && i<N-j-1; i++) { the arithmetic might overflow in one of these but not in the other. Best wishes, Duncan.

Hi, The following two segments of code are actually the same, but llvm created different cfg for them. Form1: 1 #define N 10 2 int test(int A[N][N]) 3 { 4 int i, j; 5 int result =0; 6 for(j=0; j+2<N; ++j) { 7 //for(i=0; i<j && i+j+1<N; i++) { 8 for(i=0; i<j && i<N-j-1; i++) { 9 A[i+j+1][j] = A[j + 2][j-i] + i; 10 } 11 } 12 13 for (i=0; i<N-2; ++i) 14 for (j=0;

>> 7 for(i=0; i<j && i+j+1<N; i++) { >> >> 8 for(i=0; i<j && i<N-j-1; i++) { >> >> >> Line 7 and Line 8 actually have the same expression, >> > > The expressions are logically similar, but they aren't the same to the > compiler unless some pass that recognizes these types of polynomial > equations and

> > > Having the final .ll file doesn't help debug this. If you run opt > -analyze -scalar-evolution on the .ll you pasted, it will correctly > print out the loop trip count. > > I've modified llvm-gcc to remove all the passes after indvars. > > I updated my llvm and now it works. >> > Surely the loop trip count is 256, but the Loop::getTripCount()

Just moving this branch of the thread out of the review because I don't want to derail the review thread... Kostya - why are these two cases not optimization bugs in general? (why do they only affect sanitizers?) On Mon, Nov 18, 2013 at 8:37 PM, Kostya Serebryany <kcc at google.com> wrote: > And we've been just informed by the mozilla folks about yet another case > of

On Tue, Nov 19, 2013 at 8:25 PM, David Blaikie <dblaikie at gmail.com> wrote: > Just moving this branch of the thread out of the review because I don't > want to derail the review thread... > > Kostya - why are these two cases not optimization bugs in general? (why do > they only affect sanitizers?) > The recent case from mozilla (

The root cause of those issues is the fact that sanitizers verify C++-level semantics with LLVM IR level instrumentation. For example, speculative loads are OK in IR if it can be proved that the load won't trap, but in C++ it would be a data race. On Tue, Nov 19, 2013 at 8:38 PM, Kostya Serebryany <kcc at google.com> wrote: > > > > On Tue, Nov 19, 2013 at 8:25 PM, David

On Wed, 9 Jun 2004, Vladimir Prus wrote: > Chris Lattner wrote: > > > Thanks, this works! I don't yet understand why spill code is needed there > > > at all, but I'll return to that when I have branches working correctly. > > > > I'm not sure either. Can you send the code before and after register > > allocation? > > Attached. Okay, yeah

While adding support for branch instructions in my backend, I run into a trouble. The code to handle branches looks like: void visitBranchInst(BranchInst& BI) { BB->addSuccessor (MBBMap[BI.getSuccessor(0)]); if (BI.isConditional()) BB->addSuccessor (MBBMap[BI.getSuccessor(1)]); ........... BuildMI(BB,

Chris Lattner wrote: > > Thanks, this works! I don't yet understand why spill code is needed there > > at all, but I'll return to that when I have branches working correctly. > > I'm not sure either. Can you send the code before and after register > allocation? Attached. > You might also try -regalloc=linearscan, as the default > allocator is, uhhh,

Hi, Is there anybody familiar with the code in llvm/lib/Transforms/Utils/SimplifyCFG.cpp? The function FoldBranchtoCommonDest() (line 1422) has the comment as following: "/// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a branch, /// and if a predecessor branches to us and one of our successors, fold the /// setcc into the predecessor and use logical operations to pick

On Tue, Nov 19, 2013 at 9:05 PM, Kuperstein, Michael M < michael.m.kuperstein at intel.com> wrote: > My $0.02 - I'm not sure the transformation introduces a data race. > > To the best of my understanding, the point of the C++11/C11 memory model > is to allow a wide array of compiler transformations - including > speculative loads - for non-atomic variables. > I believe

Hi, I am writing a loop pass to replace the backedge with an edge from latch to exit. Now I just replace the terminator of latch with another BranchInst, and the loop will not be a loop after my pass. However, it turns out a failure of loopverify after executing my pass: opt: ~/llvm/llvm-trunk/include/llvm/Analysis/LoopInfoImpl.h:297: void llvm::LoopBase<N, M>::verifyLoop() const [with

Hi all, I committed a first cut at blockless Givens/Whens/Thens to RSpec''s trunk: cd /path/to/rspec/project svn up cd rspec bin/spec examples/story/calculator.rb Take a look at examples/story/calculator.rb to see what''s going on. Needs docs!!!! Thoughts welcome. I''ve also got a cut at the plain text parser checked in, but it''s not hooked up to anything

Chris Lattner wrote: > On Tue, 8 Jun 2004, Vladimir Prus wrote: > > While adding support for branch instructions in my backend, I run into a > > trouble. The code to handle branches looks like: > > The machine code after instruction selection is: > > > > entry (0x8681458): > > %reg1024 = load <fi#-1> > > %reg1025 = load

On Wed, 9 Jun 2004, Vladimir Prus wrote: > > I assume that the two unconditional gotos are just test code, right? If > > not, the second one is dead. > > Yes, in the final form there will be "iflt" instruction before the first goto, > making it conditional. Ah, ok :) > > > The code after "goto" is disturbing. It looks like spill code, but

This isn''t specific to RSpec, but is hopefully on-topic for this list. I like (especially when "ping pong pairing") to write a spec, then write the smallest amount of code I can to pass it (especially when "ping pong pairing"). Sometimes this means hard-coding a return value, which means another spec is needed to prove that the code is really behaving as it

On Tue, Nov 19, 2013 at 8:38 AM, Kostya Serebryany <kcc at google.com> wrote: > > > > On Tue, Nov 19, 2013 at 8:25 PM, David Blaikie <dblaikie at gmail.com> wrote: > >> Just moving this branch of the thread out of the review because I don't >> want to derail the review thread... >> >> Kostya - why are these two cases not optimization bugs in

On Tue, 8 Jun 2004, Vladimir Prus wrote: > While adding support for branch instructions in my backend, I run into a > trouble. The code to handle branches looks like: > The machine code after instruction selection is: > > entry (0x8681458): > %reg1024 = load <fi#-1> > %reg1025 = load <fi#-2> > setcc %reg1024, %reg1025 >

What I'm trying to say is that according to my understanding of the C++11 memory model, even in that small reproducer, the store to g and the load from g are in fact a data race. (This is regardless of the fact the load is protected by a branch that is not taken.) From: Kostya Serebryany [mailto:kcc at google.com] Sent: Tuesday, November 19, 2013 19:46 To: Kuperstein, Michael M Cc: Evgeniy