Displaying 20 results from an estimated 30000 matches similar to: "[LLVMdev] Constraints"
2008 Jun 18
1
[LLVMdev] Constraints
On Wednesday 18 June 2008 01:30, Evan Cheng wrote:
> On Jun 17, 2008, at 1:36 PM, David Greene wrote:
> > Can someone explain the Constraints system in X86*.td?
> >
> > For example:
> >
> > let Constraints = "$src1 = $dst"
> >
> > This replaces isTwoAddress (according to svn logs), which I gather
> > is how
> > two-address
2008 Jun 18
0
[LLVMdev] Constraints
On Jun 17, 2008, at 1:36 PM, David Greene wrote:
> Can someone explain the Constraints system in X86*.td?
>
> For example:
>
> let Constraints = "$src1 = $dst"
>
> This replaces isTwoAddress (according to svn logs), which I gather
> is how
> two-address instructions used to be marked for X86.
You're right. This is the same as isTwoAddress, just more
2013 Jan 23
4
[LLVMdev] Instruction Constraints Question
We've discovered a problem in the AVX2 gather patterns X86InstrSSE.td.
According to the AVX2 manual, no two of the destination register, vector
index register and mask register can be the same. The patterns in
X86InstrSSE.td are missing this constraint and it's possible to generate
an illegal instruction.
It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
and
2008 Sep 23
0
[LLVMdev] A question about instruction operands.
sanjiv gupta wrote:
> I have a question:
> In the pattern below from X86
>
> def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
> "inc{b}\tdst",
> [(set GR8:$dst, (add GR8:$src, 1))]>;
>
> Since we are emitting only "inc $dst",
> What makes sure that the $src and $dst are same register?
>
> - Sanjiv
It's enclosed
2012 Oct 04
1
[LLVMdev] RegisterClass constraints in TableGen
Hi,
I've come across a problem while working on an LLVM backend for a new
target architecture.
This architecture has two single-ported register files. Each instruction
can only read one operand from each register file, but can write to either.
I tried implementing it naïvely in TableGen with two definitions per
instruction, so I had:
def AllRegs : RegisterClass< ... (add interleave
2013 Jan 23
0
[LLVMdev] Instruction Constraints Question
> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
> rules.
You can emulate such constraints via early clobbing. Just mark dst as
early clobbing.
> Is there another mechanism to suport a constraint
2007 Mar 01
1
[LLVMdev] ISel using an operand as both source and destination
On Thu, 1 Mar 2007, Christopher Lamb wrote:
> I see in the x86 InstInfo.td the following for the INC instructions:
>
> def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
> [(set GR8:$dst, (add GR8:$src, 1))]>;
>
> Which seem to have the same restriction that I'm trying to implement,
> but I don't understand how this
2013 Jan 23
3
[LLVMdev] Instruction Constraints Question
>> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
>> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
>> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
>> rules.
> You can emulate such constraints via early clobbing. Just mark dst as
> early clobbing.
How would that (or any early
2013 Jan 23
0
[LLVMdev] Instruction Constraints Question
On Wed, Jan 23, 2013 at 4:40 PM, Tim Northover <t.p.northover at gmail.com>wrote:
> >> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
> >> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
> >> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
> >> rules.
> > You can
2004 Dec 03
2
[LLVMdev] Adding xadd instruction to X86
Chris Lattner wrote:
> On Thu, 2 Dec 2004, Brent Monroe wrote:
>
>>I'm trying to add the xadd instruction to the X86 back end.
>>xadd r/m32, r32
>>exchanges r/m32 and r32, and loads the sum into r/m32. I'm
>>interested in the case where the destination operand is a
>>memory location.
>>
>>I've added the following entry to
2018 Nov 07
2
how to add a instruction
Hi,every one.
I' in trouble again.
I want add a new intrinsic mapping a new instruction.
I add the int_x86_max_qb as fllowing:
def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Commutative]>;
BUILTIN(__builtin_x86_max_qb, "iii", "")
I define the intrinsic as Pseudo instruction,it
2013 Jan 23
2
[LLVMdev] Instruction Constraints Question
Anton Korobeynikov <anton at korobeynikov.info> writes:
>> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
>> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
>> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
>> rules.
> You can emulate such constraints via early clobbing. Just
2008 Sep 23
3
[LLVMdev] A question about instruction operands.
I have a question:
In the pattern below from X86
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
"inc{b}\tdst",
[(set GR8:$dst, (add GR8:$src, 1))]>;
Since we are emitting only "inc $dst",
What makes sure that the $src and $dst are same register?
- Sanjiv
2012 Nov 16
2
[LLVMdev] Operand order in dag pattern matching in td files
Hi,
I have a simple question w.r.t the order of operands used in dag
pattern matching in target files. Some of them seem intuitive. But I
want to get it clarified anyway. I am using a pattern from
X86InstrFMA.td in the below example. Consider FMA3 pattern
(simplified).
let Constraints = "$src1 = $dst" in {
multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill,
Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub
2020 May 12
2
BPF tablegen+codegen question
In BPF, an ADD instruction is defined as a 2 register instruction:
0x0f. add dst, src. dst += src
In BPFInstrInfo.td this kind of ALU instruction is defined with:
def _rr : ALU_RR<BPF_ALU64, Opc,
(outs GPR:$dst),
(ins GPR:$src2, GPR:$src),
"$dst "#OpcodeStr#" $src",
[(set
2018 Nov 14
2
Fw: How to define an instruction
--------- Forwarded Message ---------
From: Tianhao Shen <17862703959 at 163.com>
Date: 11/14/2018 09:31
To: craig.topper at gmail.com <craig.topper at gmail.com>
Subject: Re: [llvm-dev] How to define an instruction
Hi, Craig
Thank you for replying to me.
I guess that you misunderstand my meaning about "can'r run". I just want to run my instruction by LLVM using the
2012 Nov 16
0
[LLVMdev] Operand order in dag pattern matching in td files
On 16 November 2012 13:41, Anitha B Gollamudi <anitha.boyapati at gmail.com> wrote:
> Hi,
>
> I have a simple question w.r.t the order of operands used in dag
> pattern matching in target files. Some of them seem intuitive. But I
> want to get it clarified anyway. I am using a pattern from
> X86InstrFMA.td in the below example. Consider FMA3 pattern
> (simplified).
>
2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Bill,
> Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
> define other classes, but with using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub
2018 Nov 14
2
Fw: How to define an instruction
Thank you for answering my confusion.
I have another questions.
If I add really instructions instead intrinsics ,can I reach my purpose?
I guess ,the answer is "can't". I don't find the anything about how machine to do about instructions,especially "ALU" instructions.
Thank you again,
Tianhao Shen
On 11/14/2018 13:42,Craig Topper<craig.topper at gmail.com>