similar to: [LLVMdev] want to use CallGraph Pass in llc

Paul, On Jun 2, 2008, at 12:38 AM, Paul Arndt wrote: > Hi all, > > the CallGraph pass is only available in opt. Is there any > substantial reason > for that? Or is it only because it seems not to be useful for llc? No, that's not true. > I want to use it in an backend that is derived from the CBackend. I > need the > information what functions are called in

Hi all, I too am getting this error for x86_64 when I am trying to use the Data Structure Analysis ...I svn upped both the llvm main branch and the poolalloc today in the morning and recompiled everything from scratch : $ opt -load /home/pprabhu/llvm/llvm-install-x86-64/lib/libpoolalloc.so -ds-aa < o.bc opt: /home/pprabhu/llvm/llvm/lib/VMCore/PassManager.cpp:1418: virtual void

Hello, LLVM asserts in the following scenario. Say there are three passes: A, B, C. C requires A and B; B requires A; and B does not preserve A. A valid pass ordering would be A B A C. However, opt gives the following assertion: $ opt -load libPassTest.so foo.bc -f -o /dev/null -c -debug-pass=Structure opt: /u/loc/kevin/llvm/llvm/lib/VMCore/PassManager.cpp:1424: virtual void

Dear Prakash, Yes, DSA is still in active use, although nobody else uses the -ds-aa pass as far as I know. I tried the below sample (although ds-aa should be in libLLVMDataStructure.so and not libpoolalloc.so), and I get the same error. I've seen similar problems with other passes in our work here. My guess is that -ds-aa is requiring two passes that claim to invalidate each other; this

Dear Prakash, I believe I've fixed the problem you were having with ds-aa. Please update your poolalloc tree, recompile, and let me know if it works. -- John T. Criswell, John T wrote: > [snip] > > ________________________________________ > From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] On Behalf Of Prakash Prabhu [prakash.prabhu at gmail.com] > Sent:

Hi, I am trying to use the poolallocator. More specific, I am trying to play around with the pointer compression pass. Though, I get assertion failures for the pass dependencies. This is when it in PointerCompress::getAnalysisUsage tries to register the the BU pass as required. I.e. when AU.addRequired<CompleteBUDataStructures>(); is called. $ opt -f -load

Dear all, I would like to use the PostDominatorTree in ArgPromotion. I did not find an example of how to use function level analysis inside CallGraphSCCPass. I tried to follow an example of how to use function-level pass in a module pass, but I hit "llvm_unreachable" in PMDataManager::addLowerLevelRequiredPass. What would be a proper way to make PostDominatorTree available in

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This

Hi,It seems inliner does not take into account if a call is inside a loop. I'm trying to figure out if loop-info can be made available to the inliner. When I try to add LoopInfoWrapperPass to Inliner.cpp, diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cppindex 568707d..cb51ea8 100644--- a/llvm/lib/Transforms/IPO/Inliner.cpp+++

Can anyone explain what this means? llvm/include/llvm/PassManagers.h:232: virtual void llvm::PMDataManager::addLowerLevelRequiredPass(llvm::Pass*, llvm::Pass*): Assertion `0 && "Unable to handle Pass that requires lower level Analysis pass"' failed. -Dave

I've never been able to figure this one out: llvm/lib/VMCore/PassManager.cpp:938: virtual void llvm::PMDataManager::addLowerLevelRequiredPass(llvm::Pass*, llvm::Pass*): Assertion `0 && "Unable to handle Pass that requires lower level Analysis pass"' failed. In the past, I've resolved this by disabling random addRequired calls in the offending Pass, even when

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis

Hi all: I apologize if this is a stupid question, but I haven't found a direct statement of what kinds of requirements the Pass Manager imposes on pass dependency graphs. I found a number of bug reports related to unschedulable passes (e.g. "Unable to schedule pass" asserts from the pass manager), but it isn't always clear if these are true bugs in the scheduling algorithm

hi again :) On Tue, Apr 13, 2010 at 8:57 AM, ether zhhb <etherzhhb at gmail.com> wrote: > hi john, > > thanks very much, i will try it out. > > --best regards > ether > > > On Mon, Apr 12, 2010 at 10:03 PM, John Criswell <criswell at uiuc.edu> wrote: > >> ether zhhb wrote: >> >>> hi all, >>> >>> i have some thing

On Mon, Apr 12, 2010 at 6:41 PM, ether zhhb <etherzhhb at gmail.com> wrote: > that's because FunctionPass implement the "addLowerLevelRequiredPass" > function, but others not. > > so, is there any special reason that only "addLowerLevelRequiredPass" is > allow? > There is no reason to not allow it. It is not done because there was not any use. If

FYI - There is currently an architectural issue which prevents the SCC pass manager (which runs the inliner) from relying on Function or Loop analysis passes. This is the primary motivation of the pass manager rewrite that Chandler Carruth has been working on for the last two years. He's getting relatively close to that project being done, but until then you are going to be effectively

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm

Devang Patel wrote: > On Mon, Apr 12, 2010 at 6:41 PM, ether zhhb <etherzhhb at gmail.com> wrote: > > >> that's because FunctionPass implement the "addLowerLevelRequiredPass" >> function, but others not. >> >> so, is there any special reason that only "addLowerLevelRequiredPass" is >> allow? >> >> > >

When migrating my project to 2.9, I've encountered a strange segfault where if a ModulePass's getAnalysisUsage adds LoopInfo and DominatorTree, then llvm::PMTopLevelManager::findAnalysisUsage will segfault. What's odd is that if I rearrange this (add required for DominatorTree before LoopInfo), it does not segfault. I realize that LoopInfo requires and preserves DominatorTree, but this

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only