similar to: [LLVMdev] PPC Isel complex patterns

They are all Alpha/PowerPC codegen related. Running /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/dg.exp ... FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll: NODE: 0x8582a40: i32,ch = CopyFromReg 0x8582980:1, 0x85829c0 Abort trap (core dumped) FAIL: /usr/home/jeffc/llvm/obj/../test/Regression/CodeGen/Alpha/bsr.ll: NODE: 0x85823c0:

On Mar 16, 2006, at 8:47 PM, Chris Lattner wrote: > On Thu, 16 Mar 2006, Eric Kidd wrote: >> The duplicate loads appear at the top of the %regex6 and %regex2 >> blocks below. I've tried various alias analysis implementations >> either alone or in combination. > > LICM doesn't remove common subexpressions, also -load-vn doesn't > affect LICM. Try

On 1/7/2016 5:54 PM, Phil Tomson wrote: > I got it to compile by changing to: > def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, > SDTCisSameAs<0, 1>]>; > def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; > > let Uses= [GRP] in { > def RelAddr : XSTGPseudo< (outs GPRC:$dst), >

I'm trying to figure out what this error message means: error: In RelAddr: Top-level forms in instruction pattern should have void types The definitions it's complaining about: //===----------------------------------------------------------------------===// // RELADDR //===----------------------------------------------------------------------===// def SDT_RELADDR :

What about ARM target ? I mean iPhone/iPod Touch has an ARM11 with a FPE and a VFPE. Does llvm-gcc 2.2 generates better code for them ? I'm a bit disappointed about the llvm-gcc 2.0 I tried for my iPod Touch as I saw it generated ARM code not very optimically : r7(apparently used like a frame pointer even when -fomit-frame-pointer is given) largely overused, generated code like "mov

On Mar 17, 2006, at 7:54 AM, Eric Kidd wrote: > Unfortunately, this generates really weird code on the LLVM 1.6 > PowerPC backend: > > LBB_matches_1: ; regex6 > lbz r4, 0(r3) > LBB_matches_2: ; NodeBlock > rlwinm r5, r4, 0, 24, 31 > cmplwi cr0, r5, 98 > blt cr0, LBB_matches_4 ; LeafBlock > LBB_matches_3: ; LeafBlock1 >

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne-

I'm getting this incompatible type assertion when I run tblgen on my .td files: llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X, Y*>::ret_type llvm::cast(Y*) [with X = llvm::DefInit; Y = llvm::Init; typename llvm::cast_retty<X, Y*>::ret_type = llvm::DefInit*]: Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible

But don't the defs for ADDR_RR and ADDR_RI also contain dags? def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; Do I need to create some other intermediate node type for a shifted address? Phil On

I'm starting to look into binary instruction encodings in TableGen, and I'm a bit confused on how the instruction fields are populated. Perhaps I'm just being dense, but I cannot see how SDAG operands are translated into the encoding fields. Can someone please explain the following snippet from the PPC back-end. The AND instruction in PPC is defined as: 1011 def AND :

On Mon, Sep 26, 2016 at 2:24 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 9/26/2016 3:58 PM, Phil Tomson wrote: > >> But don't the defs for ADDR_RR and ADDR_RI also contain dags? >> >> def ADDR_RR : Addr< 2, "SelectAddrRegReg", >> (ops GPRC:$base, GPRC:$offsetreg) >; >> def ADDR_RI :

Cool, that worked. New patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; >

On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote: > I'm starting to look into binary instruction encodings in TableGen, and I'm > a bit confused on how the instruction fields are populated. Perhaps I'm > just being dense, but I cannot see how SDAG operands are translated into > the encoding fields. Can someone please explain the following snippet from

Hi, In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register: class isDOT { list<Register> Defs = [CR0]; bit RC = 1; } and this gets used on instructions such as: def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral,

On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote: > > I'm starting to look into binary instruction encodings in TableGen, and > I'm > > a bit confused on how the instruction fields are populated. Perhaps I'm > > just being dense, but I cannot see how SDAG

On Tue, Jul 24, 2012 at 8:46 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Jul 24, 2012, at 3:52 PM, Justin Holewinski < > justin.holewinski at gmail.com> wrote: > > On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com>wrote: > >> On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote: >> > I'm

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction has no results. It only alters the CPSR (current program

On Jul 24, 2012, at 3:52 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com> wrote: > On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote: > > I'm starting to look into binary instruction encodings in TableGen, and I'm > > a bit confused on how the instruction

On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > $label), > "cmpw $rA, $rB\n\tbne- La${label}_exit", > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > $label)]>; > } > > ...and I can't figure out the syntax for that. Any suggestions? Hi

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the