similar to: [LLVMdev] Obligatory monthly tail call patch

Dear LLVM developers, I am a developer of SML#, an ML-style functional programming language developed at Tohoku University. Currently we are intending to use LLVM as the backend of our SML# compiler in our upcoming release, and have rewritten our frontend and runtime so that they can cooperate with LLVM. LLVM works extremely fine with our SML# compiler. We are grateful to LLVM community for

The patch is in http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080421/061548.html . Okay to commit :) On Thu, Apr 24, 2008 at 7:35 PM, Arnold Schwaighofer <arnold.schwaighofer at gmail.com> wrote: > Another round :) > > I'll post the patch to llvm-commits cause i guess people might get > annoyed by my series of patches :). > > On Tue, Apr 22, 2008 at

Another round :) I'll post the patch to llvm-commits cause i guess people might get annoyed by my series of patches :). On Tue, Apr 22, 2008 at 10:34 PM, Evan Cheng <evan.cheng at apple.com> wrote: . >> +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, >> ... > That's fine. Please break it into two parts and move the target > independent part

Hi Katsuhiro, Thanks very much for taking the time to dig into this and produce a patch. Is there any chance you could make a couple of tweaks? > This bug is due to wrong computation of stack object indices by the > x86 backend. The attached patch indicates the wrong points. Due to > integral promotion, explicit conversion to signed integer is needed > at those points. I'm not

ola, ive been looking at adding support for an -msave-args option for use on x86_64. the short explanation of it is that it makes x86_64 function prologues store their register arguments on the stack. the purpose of this is to make the arguments trivially accessible for things like stack traces with arguments. as per https://blogs.oracle.com/sherrym/entry/obtaining_function_arguments_on_amd64,

Chris Lattner wrote: > On Sat, 13 May 2006, Vladimir Prus wrote: >> in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' >> parameter, that is not documented. >> >> Can somebody explain what does it mean? > > Basically, it gives the target more information about the spill. In > particular, it specifies the register class to use

I'm wondering if there is any option available in load() such that I can specify which variable I want to load from an RData file. I don't see such option in the help.

On my (out-of-tree) target I have 16 128-bit registers. Unaligned load/store are illegal. (must 16-bytes aligned) 8 of those registers are defined as callee-saved and 8 caller-saved. The default stack size is 4 bytes. The target implements dynamic stack realign to make sure the stack will always be aligned correctly when necessary. Yet I am still getting unaligned load/store when running this

----- Original Message ----- > From: "Hal Finkel" <hfinkel at anl.gov> > To: "Francois Pichet" <pichet2000 at gmail.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Monday, November 18, 2013 2:45:53 PM > Subject: Re: [LLVMdev] Unaligned load/store for callee-saved 128-bit registers > > ----- Original

Hi. I''ve been trying to develop a module for managing Cobbler from puppet. So, I need a custom type - cobblerdistro, which will fetch ISO from http, unpack it at desired destination and register distro with Cobbler. I have one issue with ensure => absent situation. First of all, here is my type: <code> # cat type/cobblerdistro.rb Puppet::Type.newtype(:cobblerdistro) do @doc

----- Original Message ----- > From: "Francois Pichet" <pichet2000 at gmail.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Monday, November 18, 2013 2:26:30 PM > Subject: [LLVMdev] Unaligned load/store for callee-saved 128-bit registers > > > > On my (out-of-tree) target I have 16 128-bit registers. >

----- Original Message ----- > From: "Francois Pichet" <pichet2000 at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "Chad Rosier" <mcrosier at codeaurora.org>, "Jakob Stoklund Olesen" <jolesen at apple.com>, "LLVM Developers Mailing > List" <llvmdev at cs.uiuc.edu> > Sent: Thursday, November

Hi all, We have some code in Hexagon that needs to be run on MC instructions, as well as on MI instruction. Here is some background for why we have this need: Some Hexagon instructions can be converted to a more compact bit representation, with the exact same functionality, if the properties of its operands meet certain criteria. Thus on the MI layer, we check the properties of the

BTW I managed to get around this problem by flagging all the 128-bit registers as caller saved only. On my system, vector registers are more likely to be used on leaf functions anyway. On Thu, Nov 21, 2013 at 3:24 PM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- > > From: "Hal Finkel" <hfinkel at anl.gov> > > To: "Francois

I'm trying to understand the Win64 case of the code below, from X86RegisterInfo.cpp: // If this is x86-64 and the Red Zone is not disabled, if we are a leaf // function, and use up to 128 bytes of stack space, don't have a frame // pointer, calls, or dynamic alloca then we do not need to adjust the // stack pointer (we fit in the Red Zone). if (Is64Bit &&

Hi Tim, Thank you for your quick response. > I'm not convinced that's the best solution, at least conceptually. > SlotSize really is an unsigned quantity, and though it's unlikely we'd > like 0x80000000 to be interpreted as positive, rather than negative if > it ever does occur. I totally agree with you. I rewrote my fix and made a test case according to your

I start my porting for picoblaze,the soft cpu for fpga ,which is designed by XILINX from MSP430 porting . After some day's work , somethinig looks good , for it can generate for some simple C program: eg : int f1(int a) { return a+1; } but it failed with this : char f() { char a; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++; a++;

Hi llvmdev, I'm trying to figure how llvm remembers stack slots allotted to callee saved registers on x86. In particular, llvm pushes registers in decreasing order of FrameIdxs [1], so the offsets they get (as returned by MFI->getObjectOffset) don't directly correspond to their actual stack locations. In X86FrameLowering's emitCalleeSavedFrameMoves, when emitting DWARF

On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote: >> Ops.push_back(DAG.getConstant(1, MVT::i32)); >> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32), >> &Ops[0], Ops.size()); >> >> Isn't that the way how it is supposed to work? > > ADD does not use a chain, so there's no chain operand, or > MVT::Other result for it in an ADD

I'm having trouble with virtual registers/register allocation in my back-end. Basically the FastRegAlloc pass is generating calls to storeToStackSlot and loadFromStackSlot, in which we build new machine instructions, which are then _not_ processed by the reg allocator. I understand that BuildMI is changing the list of MachInst. that the allocator is iterating over, but we need to have a new