similar to: [LLVMdev] llvm useability?

Hi all, I have problem with specifying complex patterns in PPC Isel backend. I would like to fetch few instructions into one like that: def MatchPAT1 : Pat<(or (or (shl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)), 0xFF0000) ), (or (srl GPRC:$rA, (i32 imm:$imm24)), (and (shl GPRC:$rA, (i32 imm:$imm8)),0xFF00) )), (myinstr GPRC:$rA)>; That pattern

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2

On Thu, Oct 17, 2013 at 10:55 AM, Stephen Checkoway <s at pahtak.org> wrote: > In creating a test case for a bug fix in llvm-objdump, I noticed that it > differs in its output of pc-relative immediates from objdump: > > [secdev:/tmp] s$ cat a.s > main: > jmp .LBL0 > .LBL0: > ret > [secdev:/tmp] s$ llvm-mc -filetype=obj a.s > a.o >

I'm UNhappy to see the iPhone SDK REQUIRES an expensive iMac computer to be able freely to develop programs on iPhone/iPod Touch. On 08/03/2008 00:59:55, Chris Lattner (clattner at apple.com) wrote: > I'm happy to announce that the iPhone SDK beta (released yesterday, > available on http://developer.apple.com) includes a beta version of > llvm-gcc 4.2 as part of the included

Hi In my MC6809 backend, in llvm/lib/Target/MC6809/InstPrinter/MC6809InstPrinter.cpp, I have the routine void MC6809InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); ZZ if (Op.isImm()) { int64_t Imm = Op.getImm() + 2; <<<======================== O << "$"; if (Imm

Fix the mistake for debug exception(#DB), overflow exception(#OF; generated by INTO) and int 3(#BP) instruction emulation. For INTn (CD ib), it should use type 4 (software interrupt). For INT3 (CC; NOT CD ib with ib=3) and INTO (CE; NOT CD ib with ib=4), it should use type 6 (software exception). For other exceptions (#DE, #DB, #BR, #UD, #NM, #TS, #NP, #SS, #GP, #PF, #MF, #AC, #MC, and #XM), it

Which BTQ? There are three flavors. BTQ reg/reg BTQ reg/mem BTQ reg/imm I can imagine that the reg/reg and especially the reg/mem versions would be slow. However the shrq/and versions *with the same operands* would be slow as well. There's even a compiler comment about the reg/mem version saying "this is for disassembly only". But I doubt BTQ reg/imm would be microcoded. -- Ite

Has llvm reached the point that it is useable as a mainstream c++ compiler? Are there benchmarks available comparing generated code to gcc4? My primary interest is scientific-type computing.

Dear all, I have written an assembler which reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the

On 10/12/2016 2:22 PM, Alex Bradley wrote: > > > > You probably want to look at the x86 backend; it has a lot of > instructions which involve both computation and memory. Take the > following IR, a variant of your example: > > > > define void @foo(i32 *%a, i32 *%b, i32 *%c) { > > entry: > > %0 = load i32, i32* %a, align 4 > > %1 = load i32,

The FAQ Section 7 is a very useful place for new users to find out any number of R idiosycracies. However there is no numbering on the FAQ Table of Content or on the Sections Tables of Contents. An R-help list reply of "Read FAQ 7.10" in response to a question about converting a factor to numeric is a bit cryptic. The only time 7.10 appears is after the searcher has found the entry.

In creating a test case for a bug fix in llvm-objdump, I noticed that it differs in its output of pc-relative immediates from objdump: [secdev:/tmp] s$ cat a.s main: jmp .LBL0 .LBL0: ret [secdev:/tmp] s$ llvm-mc -filetype=obj a.s > a.o [secdev:/tmp] s$ objdump -d a.o |tail -n 2 0: eb 00 jmp 2 <main+0x2> 2: c3 retq

Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them

I was starting to write a note to a prospective R-user and came to the point of explaining how to get useful introductory information on R. After mentioning the Into and the FAQs I went on to try to explain how to use a lot of the contributed information. However I realised that there seems to be no direct way to get to Other Publications or Contributed Documenation. The best I have seen is

Yes, I know. It's just when I see "happy", "Apple" and "iPhone SDK" on an Apple employee's mouth here, I felt a strong urge on the spur of moment to express my discontent towards Apple people who think they should make us buy their iMac just to be able to code freeware applications on iPhone. I've been waiting for so long time until an official SDK is

On Wed, Jul 10, 2013 at 7:15 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Jul 10, 2013, at 6:54 PM, Stephen Checkoway <s at pahtak.org> wrote: > > On Jul 10, 2013, at 17:44, Jim Grosbach <grosbach at apple.com> wrote: > > The length specifier is, as I understand it, required when the instruction > references memory but is optional (and inferred from

Eli Friedman wrote: > The reason it's the right thing to do is that the mem/imm forms of > btsw and btsl have exactly the same semantics. The Intel documentation implies that this is the case: > If the bit base operand specifies a memory location, it represents the address of the byte in memory that contains the bit base (bit 0 of the specified byte) of the bit string (see Figure

On Jul 10, 2013, at 6:54 PM, Stephen Checkoway <s at pahtak.org> wrote: > On Jul 10, 2013, at 17:44, Jim Grosbach <grosbach at apple.com> wrote: >> The length specifier is, as I understand it, required when the instruction references memory but is optional (and inferred from the registers) for the register variants. >> >> The best reference I know of for the

Some instructions, like "add $imm8, r/m16"/"MOV $imm32, r/m64" require the src immediate operand be sign-extented befere the op is executed, but this is omitted in the current Xcode. The patch fixes this. The patch also fixes an issue in handling address-size override prefix, and fixes an issue in get_immediate(). Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>

Hi, I am facing an issue with tablegen. tablegen complains about not finding a register when % is used in the instruction string. error: unable to find register for '' (which matches register prefix) I have copied an example (not the original). Note that i added %prefix_ before $sp register. Tablegen seems to interpret % as placeholder for inserting register. Is there any way to make