Displaying 20 results from an estimated 5000 matches similar to: "[LLVMdev] ComplexPattern in child ISel nodes"
2008 Jan 02
0
[LLVMdev] ComplexPattern in child ISel nodes
On Dec 30, 2007, at 9:04 PM, Christopher Lamb wrote:
> Currently tablegen emits a rather surprising match code for the
> following case:
>
> Suppose we have a pattern that uses a ComplexPattern to match an
> operand. This pattern then appears as a child pattern in a
> different pattern.
> Pattern 1: (N1 ComplexPattern:OP)
> Pattern 0: (N0 (N1 ComplexPattern:OP))
>
2008 Jan 03
1
[LLVMdev] ComplexPattern in child ISel nodes
On Jan 1, 2008, at 9:29 PM, Evan Cheng wrote:
>
> On Dec 30, 2007, at 9:04 PM, Christopher Lamb wrote:
>
>> Currently tablegen emits a rather surprising match code for the
>> following case:
>>
>> Suppose we have a pattern that uses a ComplexPattern to match an
>> operand. This pattern then appears as a child pattern in a
>> different pattern.
2009 Jan 14
2
[LLVMdev] Use two ComplexPatterns (possible bug of TableGen?)
It seems that it's not allowed to two same 'ComplexPattern's in a 'def',
because TableGen generate the same variable names for the two ComplexPatterns.
If I understand the source code of TableGen correctly, it's not designed to
use more than one ComplexPattern instance (no matter they are the same or not).
In the following example, two 'regsw' are used to match
2010 Jan 19
1
[LLVMdev] ComplexPattern
Hi,
I was wondering if someone could explain precisely what the
ComplexPattern tablegen class does?
Here's the first line of the definition (from TargetSelectionDAG.td) for
reference:
class ComplexPattern<ValueType ty, int numops, string fn,
list<SDNode> roots = [],
list<SDNodeProperty> props = [],
2009 Jan 14
0
[LLVMdev] Use two ComplexPatterns (possible bug of TableGen?)
Alex schrieb:
> It seems that it's not allowed to two same 'ComplexPattern's in a 'def',
> because TableGen generate the same variable names for the two ComplexPatterns.
> If I understand the source code of TableGen correctly, it's not designed to
> use more than one ComplexPattern instance (no matter they are the same or not).
I've run into this too, the
2006 Jul 03
2
help a newbie with a loop
Hi,
I am new in R and stumbled on a problem my (more experienced) friends
can not help with with. Why isnt this code working?
The function is working, also with the loop and the graph appears,
only when I build another loop around it (for different values of p) ,
R stays in a loop?
Can't it take more then 2 loops in one program?
powerb<-function(x,sp2,a,b,b1,m)
{
2008 Oct 29
2
Help using tapply with multiple variables
Dear list,
I have the function (as a simple example, which is actually part of a
larger function)
pres.test<-function(N0=N0, N1=N1)
{
dt<-5
r<-log(N1/N0)/dt
r
}
which calculates the annual growth rates in a population
Where N0 is the population classified into age intervals, say 5
years, at time=1995, and N1 is the population by 5 year age classes
at time=2000.
2009 Jan 15
2
[LLVMdev] Use two ComplexPatterns (possible bug of TableGen?)
On Wednesday 14 January 2009 18:59:03 Brandner Florian wrote:
> I have a patch against llvm 2.4 that fixes this issue, but did not have
> the time to post the patch here. I'll do so by tomorrow.
here is the patch, still against llvm 2.4. I had a short look on trunk, but it
seems that there are several conflicts. Maybe a tablgen expert should have a
look at this - I also do not know if
2009 Mar 18
2
[LLVMdev] Selecting FrameIndex
Hi All
I'm having nightmares with FrameIndexes during my backend development :(
I have ComplexPatterns defined for my two addressing modes (RR and
RI). Most of the time, FrameIndex operands appear to be on load/store
nodes, in which case everything works fine as my custom addressing
modes matchers work fine.
Unfortunately, I now have an add node which has a FrameIndex operand
(this results
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
I'm trying to write a store pattern that accepts both i32 and f32,
however, when tablegen generates the code, it only generates the code
for i32 only.
def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
def MEM : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops GPR, GPR);
}
def global_st :
2002 Aug 07
2
indexing matrices with dimnames?
I've got a covariance matrix that I'd like to index using the
dimnames:
> vcov1
n0 x0 s n1 n2
n0 82.43824759 1.839505e-02 -4.975196e-01 2.882394e+03 -2.615986e-01
x0 0.01839505 6.134010e-03 -7.695922e-04 -6.373946e+01 6.086321e-03
s -0.49751964 -7.695922e-04 9.638943e-03 3.406594e+02 -3.173671e-02
n1 2882.39407745
2019 Jul 21
6
[RFC] A new multidimensional array indexing intrinsic
Hello,
We would like to begin discussions around a new set of intrinsics, to
better express
multi-dimensional array indexing within LLVM. The motivations and a
possible design
are sketched out below.
Rendered RFC link here
<https://github.com/bollu/llvm-multidim-array-indexing-proposal/blob/master/RFC.md>
Raw markdown:
# Introducing a new multidimensional array indexing intrinsic
## The
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote:
> There certainly are wishlist items for TableGen and TableGen-based
> instruction descriptions, though I don't know of an official list.
> Offhand,
> a few things that come to mind are the ability to handle nodes with
> multiple results,
Is there an official workaround, BTW?
- Volodya
2019 Mar 13
2
llvm combines "ADD frameindex, constant" to OR
Hi all,
I've been working on a backend of our architecture and noticed llvm performs
following combining although one of operands is FrameIndex.
Combining: t114: i64 = add FrameIndex:i64<0>, Constant:i64<56>
Creating new node: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56>
... into: t121: i64 = or FrameIndex:i64<0>, Constant:i64<56>
This
2006 Jun 14
2
Bug or not? (PR#8977)
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Hi,
I am writing this email, because I am not sure if the issue I have
discovered is a bug or not.
For a few days I have been fiddling around with a small program that
calculates the reflectance of
2019 Jul 22
2
[RFC] A new multidimensional array indexing intrinsic
> It seems that the main advantage of your proposal is that it would allow for non-constant strides (i.e. variable length arrays) in dimensions other than the first one. Do these appear frequently enough in the programs that you're interested in to be worth optimizing for?
Yes - at least in Chapel (which is one of the motivating languages)
these are very common.
In other words, typical
2019 Jul 03
3
optimisation issue in an llvm IR pass
Hi Craig,
On 03.07.19 17:33, Craig Topper wrote:
> Don't the CreateICmp calls return a Value* with an i1 type? But then
> they are added to an i8 type? Not sure that works.
I had that initially:
auto cf = IRB.CreateICmpULT(Incr, ConstantInt::get(Int8Ty, 1));
auto carry = IRB.CreateZExt(cf, Int8Ty);
Incr = IRB.CreateAdd(Incr, carry);
it makes no difference to the generated assembly
2019 Jul 22
2
[RFC] A new multidimensional array indexing intrinsic
We could also simply extend the existing inrange mechanism to
non-constantexpr GEPs. It would remove an inconsistency in the
semantics, be relatively straight forward, and solve the motivating
example.
(I didn't read the proposal in full, so there may be other examples it
doesn't solve.)
Philip
On 7/22/19 10:01 AM, Peter Collingbourne via llvm-dev wrote:
> The restrictions of
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
On Sep 23, 2008, at 10:44 AM, Villmow, Micah wrote:
> I’m trying to write a store pattern that accepts both i32 and f32,
> however, when tablegen generates the code, it only generates the
> code for i32 only.
>
> def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
> def MEM : Operand<i32> {
> let PrintMethod = "printMemOperand";
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote:
> Bill Wendling wrote:
>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
>>
>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>>>
>>>> Our architecture has 1-bit boolean predicate registers.
>>>>
>>>> I've defined comparison
>>>>
>>>> def