similar to: [LLVMdev] Instruction selector internals

Hi there first of all, many thanks to some people out there for their advice on building LLVM on Cygwin (this would be Aaron Gray, Reid Spencer, Tanya and Chris Lattner i suppose). LLVM 2.1 seems to build in debug mode on my "old" Cygwin (1.5.15). At least everything except tblgen is build. For tblgen i use the supplied mingw binaries, many thanks for that! I would like now to ask you

I'm trying to replace procmail with deliver but I'm having problems with the group part of things. I keep getting: Aug 29 16:44:19 dingbat deliver(mimo): open(/var/mail/.temp.dingbat.3969.d1689935a308e0dd) failed: Permission denied Aug 29 16:44:19 dingbat deliver(mimo): file_lock_dotlock() failed with mbox file /var/mail/mimo: Permission denied My primary group is mimo and I think

> > It's a pattern matcher operating on DAG's. Target independent nodes > in, target specific nodes out. I guess this is general enough. So the restriction lies in the implementation language and not the pattern matcher itself. I'll spend some (a lot of) time to understand the backend-specific issues that are of particular interest to me. Eventually, I'll get back with a

Hi, I'm trying to get the drac plugin working (again) but I'm stuck with the following message: Restarting IMAP/POP3 mail server: dovecotEDRAC: net_ip2addr() failed: Operation not permitted This is on a Debian Squeeze box, dovecot version 1.2.15-7, drac version 1.12 Looking at the source it should print the IP in the brackets of net_ip2addr. The fact that it's just empty made me

Hello all, We are working on a new project idea for xen platform. I have summarized as well as given detailed description of what we are trying to achieve. I request your comments on the feasibility of this project. Also I have pointed some relevant works which I feel is primitive considering the goal we are trying to achieve. I request to point me to relevant links if there are any other works

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Hi everyone, llvm is great! But there is one exception ;) llvm components are generally fast, but instruction selection is slooow. Let me explain. I am developing a toolkit for building virtual machines which can automatically generate a JIT compiler using the interpreter specification. llvm does the hard work of machine code generation. (Thanks to you all) I discovered that JIT compilation is

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",

Thanks all, for all the pointers. I'd read some of them, but others are new. Jim, I'd certainly appreciate the chance to get together at the dev conference. I think y'all's ideas of a stub back end sound good, though I can appreciate the maintenance difficulties. Karen's idea for a new design guide is also good, though I think the idea of looking at other back ends for examples

On Mon, 2 Oct 2006, Roman Levenstein wrote: >>> Wouldn't it be possible and even more clean to have just one >>> description like (I use a pseudo-description here): >>> >>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst, >>> (i8mem|i16mem|i32mem):$src), >>> "mov{b} {$src, $dst|$dst, $src}", []>,

On 25 September 2013 12:28, Sean Silva <chisophugis at gmail.com> wrote: > > > > On Wed, Sep 25, 2013 at 7:02 AM, Renato Golin <renato.golin at linaro.org> > wrote: >> > (Devil's advocate, but half serious): > > It may be a good idea to require that the dummy backend is kept up to date, > as a way to keep a pulse on changes to the interfaces between

Dear friends, I have been using the SUIF Machine infrastructure for sometime. Some optimizations are available without using a target machine, i.e. at the SUIFvm level. At this level you have "infinite" registers. Other optimizations, including analyses as for profiling require the use of a target library, a complete backend. It is very sad, that they have discontinued their MIPS

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Nikolaos Kavvadias wrote: > Dear friends, > > I have been using the SUIF Machine infrastructure for sometime. Some > optimizations are available without using a target machine, i.e. at the > SUIFvm level. At this level you have "infinite" registers. Other > optimizations, including analyses as for profiling require the use of a > target library, a complete

Alain, > Thanks. However, I'm specifically interested in using the MinGW compiler > shipped with Cygwin (i.e. "gcc -mno-cygwin") and using Cygwin tools > (make, ...). Of course, I could probably install MSYS/MinGW just to > compile LLVM and produce the libraries. The short answer is: don't use cygwin shell with mingw compiler to build LLVM. Reason actually is:

Hi there i would like to ask a few questions to the developers responsible for the register allocator(s) design in LLVM (Fernando and other people). First of all, congrats on providing more than one option for register allocation. Now to the questions: 1. I can see the standard algorithms (bigblock, linearscan -- good choice for the JIT and for general use as well, and the other algorithms).

I have been working on improvements to TableGen's DAG Isel matcher backend. This has led me to thinking about ways to speed up the compile-time interpreter of the instruction selection matcher table. Is this worth my time, given Fast Isel and the upcoming Global Isel selector?

I just ran across this bug when trying to re-create Ben Nolan''s behaviour.js with prototype and was wondering if anyone had fixed it before I went re-inventing the wheel :) Thanks! -Jeremy -- Jeremy Kitchen ++ kitchen-RA8HwDor7flnDGu+y90WmgC/G2K4zDHf@public.gmane.org http://ipaction.org/ -- defend your rights to fair use _______________________________________________

Hi Guys, I have a taget instruction which take a vec4 and returns a vec4.( say instruction “vec4:$dst mod( vec4:$src)" ) And I want to use it to match i an ir instruction/intrinsic function( say " float:$dst llvm.irmod( vec4:$src)" which takes a vec4, output a float. I think the procedure is: when I see the intrinsic llvm.irmod, I need to call "extractlt(

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