similar to: [LLVMdev] Address of label

Hello, I want to compile a LLVM file into an executable running on ARM platform. I use LLVM 2.0 with the following command lines: llvm-as -f -o test.bc test.ll llc -march=arm -mcpu=arm1136j-s -mattr=+v6 -f -o test.s test.bc arm-linux-gnu-as -mcpu=arm1136j-s test.s With the last command, I obtain the following error: rd and rm should be different in mul The bad instruction is

Hi Mikael, You are obtaining warning, not an error, right? The most arm cores, including arm1136, can execute mul with rd = rm. So, you can ignore this warning. Lauro 2007/6/12, Peltier, Mikael <m-peltier at ti.com>: > > > > > Hello, > > > > I want to compile a LLVM file into an executable running on ARM platform. > > I use LLVM 2.0 with the following

Hello, I want to find information/documentation on how reorganize stack frame (add other information, etc.) & how add new calling convention into ARM backend? I think it is needed to modify lowering of CALL, RET & FORMAL_ARGUMENT instruction, and also to modify emitPrologue & emitEpilogue functions. What are the others things to modify in order to realize my

Hi. I'm working on a backend for the [DCPU16](https://github.com/techcompliant/TC-Specs/blob/master/CPU/DCPU.md), a fictional CPU. The main subtlety is that the bytes are 16 bits instead of 8. There is already a [working backend](https://github.com/krasin/llvm-dcpu16), but it does a lot of source modification to support 16 bit words. I try to update it to latest llvm, but it obviously

Hi Mikaël, Thanks for the patch. Some comments: 1. Please don't use tabs. 2. Index: lib/Target/ARM/ARMInstrInfo.cpp =================================================================== --- lib/Target/ARM/ARMInstrInfo.cpp (revision 14) +++ lib/Target/ARM/ARMInstrInfo.cpp (working copy) @@ -904,7 +904,8 @@ return TAI->getInlineAsmLength(MI-

Folks, I'm at the point in developing llvmc (Compiler Driver) where I need to get the details on the specific optimization arguments that the -O family of options should (by default) issue to "opt". I'm soliciting your feedback on this so I can start testing optimization. Hopefully you can provide it by early this coming week. For clarity, the -O options are currently defined

Hi all, FlexyCore, the company I am working for, use LLVM to generate binary for ARM platform. We are very fulfilled with LLVM, and FlexyCore will be pleased to contribute on this software. We need debug support in ARM binary, but, in LLVM 2.4, this support is not activated for ARM backend. Consequently, I made small modifications in order to activate it (see the patch in attach file). My

I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, -march=armv6, ...) to let the compile know the specific ARM processor, but the same issue is still there. I tried to take a look at .s file in /tmp directory, but it's already cleaned up. Is it because I enabled the optimization option when I compiled llvm? Regards, Won On Wed, Jul 8, 2009 at 1:28 PM, Dale Johannesen <dalej

Hi Evans, Currently, we have not test all debug functionnalities, this will be done with the progress of our project. Could you explain more in details (by mail if possible) what is the problem with aggregates and debugging ? Could you also provide C program or llvm source file that exposes this problem in order to see what we can do? During our roadmap progress, FlexyCore will not hesitate to

Hi all, I attempted to add an EL5.1 client to our puppet server (EL5), and after signing the client cert, got the error "Certificates were not trusted: hostname not match with the server certificate" I found the mailing list discussion and the relevant page: http://www.reductivelabs.com/trac/puppet/wiki/RubySSL-2007-006 As far as I can tell, my puppermaster''s cert CN matches

Hi, I would like to log the errors to stderr and to a file, but it doesn't seem possible for now. I tried ``` <errorlog>icecast-error.log</errorlog> <errorlog>-</errorlog> ``` but the last setting erases the previous ones so I can only print to one of them. Could you add this feature? Have a good day, Mikaël Fourrier

Hello, Mikael. > In this file, we saw that branches are realized by affecting virtually > an id to each label and use a switch in order to find the right > target. Right. > I want to know if there is another way to do this, for instance, by > accessing the address of label and to branch directly to it? As it seems to me, no (I can be mistaken, though). > In the optimized

On Jan 7, 2011, at 2:36 PM, Venkatraman Govindaraju wrote: > When I run LLC with option "-O0 -march=sparc" on following testcase, > fast register allocator crashes with "UNREACHABLE executed" error. LLC > generates code successfully with other standard register allocators > available. I haven't investigated the Sparc backend specifically but... My guess is

Thanks for the commit. FlexyCore works only on ARM EABI Linux target for now. This binary with Dwarf information could be debugged with a gdb-server 6.8 without problem on our side. If you are working on ARM Linux target, could you send us LLVM source file, and gdb version ? But if you are using ARM Darwin as Anton suggest, we are unable to test this for now. We are open to help on this

On Dec 11, 2008, at 8:23 AM, Mike-1 wrote: > > Thanks for the commit. > > FlexyCore works only on ARM EABI Linux target for now. This binary > with > Dwarf information could be debugged with a gdb-server 6.8 without > problem on > our side. Good to hear. Are you able to examine aggregates? > > > If you are working on ARM Linux target, could you send us LLVM

On Sat, 14 Aug 2004, Reid Spencer wrote: > I'm at the point in developing llvmc (Compiler Driver) where I need to > get the details on the specific optimization arguments that the -O > family of options should (by default) issue to "opt". I'm soliciting > your feedback on this so I can start testing optimization. Hopefully you > can provide it by early this coming

On Jul 8, 2009, at 12:52 PMPDT, Won J Jeon wrote: > I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, - > march=armv6, ...) to let the compile know the specific ARM > processor, but the same issue is still there. I tried to take a look > at .s file in /tmp directory, but it's already cleaned up. Is it > because I enabled the optimization option when I

Let's say I have 2 bytecode files, X.bc and Y.bc that I want to combine into Z.bc. Which of the following command sequences will produce more optimized code? Sequence 1: llvm-link -o tmp.bc X.bc Y.bc opt -std-compile-opts -o Z.bc tmp.bc Sequence 2: llvm-ld -O5 -o Z.bc X.bc Y.bc Without looking at details it seems like sequence 2 should produce the most optimized code. As a follow

Reid, I have one substantial change to suggest to this. I think the distinction between module-level and cross-module optimization is artificial and unnecessary in LLVM because transparent link-time optimization makes intra-module and cross-module optimizations indistiguishable. It *is* important to distinguish between fast and slow optimizations. Because of this, I would suggest a

Thanks. I could take a look at the lines and all of them have smull instruction like 'smull r0, r1, r0, r1'. Won On Wed, Jul 8, 2009 at 2:54 PM, Dale Johannesen <dalej at apple.com> wrote: > > On Jul 8, 2009, at 12:52 PMPDT, Won J Jeon wrote: > > I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, > -march=armv6, ...) to let the compile know the