similar to: [LLVMdev] If conversion scope

On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]

Hi all, I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering

On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement > branching on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so > I'm not exactly sure on what is the

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to

On May 24, 2011, at 12:02 AM, roy rosen wrote: > Hi, > > I was wondering if LLVM supports predicates and conditional execution. > Something like we have in IA64. > There is a register class of predicates and then every instruction may > be predicated by a register from this class. > For example: > > cmp_less p, x, y // p is a predicate which gets the result of x <

Hello. Because I experience optimizations (DCE, OoO schedule) which mess the correct semantics of the list of instructions lowered in ISelLowering from the VSELECT LLVM instruction, and these bad transformations happen even before scheduling, at later I-sel subpasses, I try to fix this problem by lowering VSELECT to only one pseudo-instruction and LATER translate it to a list of

Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Hello, I have a few questions about applying the IfConversion pass to my out-of-tree target. (1) Is it true that the IfConversion pass may only run after register allocation? I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hello. For my back end for the Connex SIMD research processor I want to implement conditional blocks (I guess the better term is predicated blocks). Predicated blocks are bordered by two instructions WHEREEQ (or WHERELT, etc) and ENDWHERE. For example, the following code executes the instructions inside the WHERE block only for the lanes where R0 == R1: EQ R0, R1;

Evan, et al., I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example: ** Before if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB

Hello everyone, I'd like to know if there is an optimization in llvm doing something like an if-conversion on the IR. I only found IfConversion.cpp which appears to only provide the desired functionality on machine code during code-generation. I want to transform branches into serial code with select-instructions as a pre-processing step for further transformations. If there is no such

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add instruction Is there support in LLVM to something

On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote: > Hi Kyle, > > my apologies for mailing you directly but it seems new user creation is > disabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may*

Ohh, that makes sense. And is the reason the first instruction doesn't get deleted because the ExpandPseudoInstructions pass occurs after Register Allocation and machine dead code elimination? -Dilan On Fri, Jul 7, 2017 at 12:37 PM Friedman, Eli <efriedma at codeaurora.org> wrote: > On 7/7/2017 12:10 PM, Dilan Manatunga wrote: > > My bad for not looking further. I'm still

Hi, On 01/23/2013 11:30 PM, Jakob Stoklund Olesen wrote: > If you can find the place that creates the duplicate MBB edge, that would be great. > Found it :) It happens in lib/CodeGen/IfConversion.cpp at the very end in MergeBlocks. I attached a small patch that should resolve that issue. Our tests now compile sucessfully even without my previous patch. regards, Stefan --------------

Hello, I'm working on a compiler based on LLVM for a SIMD architecture that supports instruction predication. We would like to implement branching on this architecture using predication. As you know the LLVM-IR doesn't support instruction predication, so I'm not exactly sure on what is the best way to implement it. We came up with some ways to do it in LLVM: - Do not add any